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    參數(shù)資料
    型號: 93C56AT-E/STG
    元件分類: PROM
    英文描述: 256 X 8 MICROWIRE BUS SERIAL EEPROM, PDSO8
    封裝: 4.40 MM, ROHS COMPLIANT, PLASTIC, TSSOP-8
    文件頁數(shù): 3/30頁
    文件大?。?/td> 551K
    代理商: 93C56AT-E/STG
    2008 Microchip Technology Inc.
    DS21794F-page 11
    93AA56A/B/C, 93LC56A/B/C, 93C56A/B/C
    2.9
    Write All (WRAL)
    The Write All (WRAL) instruction will write the entire
    memory array with the data specified in the command.
    For 93AA56A/B/C and 93LC56A/B/C devices, after the
    last data bit is clocked into DI, the falling edge of CS
    initiates the self-timed auto-erase and programming
    cycle. For 93C56A/B/C devices, the self-timed auto-
    erase and programming cycle is initiated by the rising
    edge of CLK on the last data bit. Clocking of the CLK
    pin is not necessary after the device has entered the
    WRAL cycle. The WRAL command does include an
    automatic ERAL cycle for the device. Therefore, the
    WRAL
    instruction does not require an ERAL instruction,
    but the chip must be in the EWEN status.
    The DO pin indicates the Ready/Busy status of the
    device if CS is brought high after a minimum of 250 ns
    low (TCSL).
    VCC must be
    ≥4.5V for proper operation of WRAL.
    FIGURE 2-10:
    WRAL TIMING FOR 93AA AND 93LC DEVICES
    FIGURE 2-11:
    WRAL TIMING FOR 93C DEVICES
    Note:
    After the Write All cycle is complete,
    issuing a Start bit and then taking CS low
    will clear the Ready/Busy status from DO.
    CS
    CLK
    DI
    DO
    HIGH-Z
    100
    01
    x
    x
    Dx
    D0
    High-Z
    Busy
    Ready
    TWL
    VCC must be
    ≥4.5V for proper operation of WRAL.
    TCSL
    TSV
    TCZ
    CS
    CLK
    DI
    DO
    HIGH-Z
    100
    01
    x
    x
    Dx
    D0
    High-Z
    Busy
    Ready
    TWL
    TCSL
    TSV
    TCZ
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