參數(shù)資料
型號: 93C46C-I/MSG
元件分類: PROM
英文描述: 64 X 16 MICROWIRE BUS SERIAL EEPROM, PDSO8
封裝: ROHS COMPLIANT, PLASTIC, MSOP-8
文件頁數(shù): 2/30頁
文件大小: 548K
代理商: 93C46C-I/MSG
93AA46A/B/C, 93LC46A/B/C, 93C46A/B/C
DS21749G-page 10
2008 Microchip Technology Inc.
2.8
Write
The WRITE instruction is followed by 8 bits (if ORG is
low or A-version devices) or 16 bits (if ORG pin is high
or B-version devices) of data, which are written into the
specified address. For 93AA46A/B/C and 93LC46A/B/C
devices, after the last data bit is clocked into DI, the
falling edge of CS initiates the self-timed auto-erase and
programming cycle. For 93C46A/B/C devices, the self-
timed auto-erase and programming cycle is initiated by
the rising edge of CLK on the last data bit.
The DO pin indicates the Ready/Busy status of the
device if CS is brought high after a minimum of 250 ns
low (TCSL). DO at logical ‘0’ indicates that programming
is still in progress. DO at logical ‘1’ indicates that the
register at the specified address has been written with
the data specified and the device is ready for another
instruction.
FIGURE 2-8:
WRITE TIMING FOR 93AA AND 93LC DEVICES
FIGURE 2-9:
WRITE TIMING FOR 93C DEVICES
Note:
After the Write cycle is complete, issuing a
Start bit and then taking CS low will clear
the Ready/Busy status from DO.
CS
CLK
DI
DO
1
0
1
AN
A0
Dx
D0
Busy
Ready
High-Z
TWC
TCSL
TCZ
TSV
CS
CLK
DI
DO
1
0
1
AN
A0
Dx
D0
Busy
Ready
High-Z
TWC
TCSL
TCZ
TSV
相關(guān)PDF資料
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93C46A-I/SN 128 X 8 MICROWIRE BUS SERIAL EEPROM, PDSO8
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