參數(shù)資料
型號(hào)： 93C46A-I/MC
元件分類： PROM
英文描述： 128 X 8 MICROWIRE BUS SERIAL EEPROM, PDSO8
封裝： 2 X 3 MM, 0.90 MM HEIGHT, ROHS COMPLIANT, PLASTIC, DFN-8
文件頁(yè)數(shù)： 30/30頁(yè)
文件大?。?/td> 548K
代理商： 93C46A-I/MC
2008 Microchip Technology Inc.
DS21749G-page 9
93AA46A/B/C, 93LC46A/B/C, 93C46A/B/C
2.6
Erase/Write Disable and Enable
(EWDS/EWEN)
The 93XX46A/B/C powers up in the Erase/Write Disable
(EWDS) state. All programming modes must be preceded
by an Erase/Write Enable (EWEN) instruction. Once the
EWEN
instruction is executed, programming remains
enabled until an EWDS instruction is executed or Vcc is
removed from the device.
To protect against accidental data disturbance, the EWDS
instruction can be used to disable all erase/write functions
and should follow all programming operations. Execution
of a READ instruction is independent of both the EWEN and
EWDS
instructions.
FIGURE 2-5:
EWDS TIMING
FIGURE 2-6:
EWEN TIMING
2.7
Read
The READ instruction outputs the serial data of the
addressed memory location on the DO pin. A dummy
zero bit precedes the 8-bit (if ORG pin is low or A-version
devices) or 16-bit (if ORG pin is high or B-version
devices) output string.
The output data bits will toggle on the rising edge of the
CLK and are stable after the specified time delay (TPD).
Sequential read is possible when CS is held high. The
memory data will automatically cycle to the next register
and output sequentially.
FIGURE 2-7:
READ TIMING
CS
CLK
DI
10
00
0
x
x
TCSL
1x
CS
CLK
DI
00
1
x
TCSL
CS
CLK
DI
DO
11
0
AN
A0
High-Z
0
Dx
D0
Dx
D0
Dx
D0
相關(guān)PDF資料
PDF描述
93C46AXT-I/OT 128 X 8 MICROWIRE BUS SERIAL EEPROM, PDSO6
93AA46AXT-I/MS 128 X 8 MICROWIRE BUS SERIAL EEPROM, PDSO8
93AA46AXT-I/OT 128 X 8 MICROWIRE BUS SERIAL EEPROM, PDSO6
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93C46AN 制造商:Texas Instruments 功能描述:
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93C46API 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Microwire Serial EEPROM
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