
Philips Semiconductors
PNX15xx Series
Volume 1 of 1
Chapter 5: The Clock Module
PNX15XX_SER_3
Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 3 — 17 March 2006
5-39
6
turn_off_ack
R
0
0 - Indicates if the enabled clock is running
1 - Indicates that the clock is being blocked during a frequency
change to avoid glitches
5:3
sel_clk_mbs_src
R/W
111
000: clk_mbs_src = clk_144
001: clk_mbs_src = clk_123
010: clk_mbs_src = clk_108
011: clk_mbs_src = clk_96
100: clk_mbs_src = clk_86
101: clk_mbs_src = clk_78
110: clk_mbs_src = clk_72
111: clk_mbs_src = clk_66
2:1
sel_clk_mbs
R/W
00
00: clk_mbs = 27 MHz xtal_clk
01: clk_mbs = clk_mbs_src
10: clk_mbs = 27 MHz xtal_clk
11: clk_mbs = AI_SD[3]
0
en_clk_mbs
R/W
1
1: enable clk_mbs
Offset 0x04,7114
CLK_TSTAMP_CTL
31:4
Reserved
R/W
-
To ensure software backward compatibility unused or reserved bits
must be written as zeros and ignored upon read.
3
turn_off_ack
R
0
0 - Indicates if the enabled clock is running
1 - Indicates that the clock is being blocked during a frequency
change to avoid glitches
2:1
sel_clk_tstamp
R/W
00
00: clk_tstamp = 27 MHz xtal_clk
01: clk_tstamp = Source clock (clk_108)
10: clk_tstamp = Second Clock (clk_13_5)
11: clk_tstamp = AO_WS
0
en_clk_tstamp
R/W
1
1: enable clk_tstamp
Offset 0x04,7118
CLK_LAN_CTL
31:6
Reserved
R/W
-
To ensure software backward compatibility unused or reserved bits
must be written as zeros and ignored upon read.
5
turn_off_ack
R
0
0 - Indicates if the enabled clock is running
1 - Indicates that the clock is being blocked during a frequency
change to avoid glitches
4:3
sel_lan_clk_src
R/W
00
00: clk_lan_src = UNDEF
01: clk_lan_src = PLL1
10: clk_lan_src = DDS4
11: clk_lan_src = DDS7
Table 11: CLOCK MODULE REGISTERS …Continued
Bit
Symbol
Acces
s
Value
Description