
Philips Semiconductors
PNX15xx Series
Volume 1 of 1
Chapter 12: Video Input Processor
PNX15XX_SER_3
Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 3 — 17 March 2006
12-30
31:28
Unused
-
27: 3
PSU_BASE2
R/W
Base address DMA #2
used depending on PSU_BAMODE setting
2:0
PSU_OFFSET2
R/W
Base address byte offset plane 2
bits dene pixel offset within multi pixel 64 bit words
(e.g. a 16bit pixel can be placed on any 16 bit boundary)
Offset 0x10 634C
Target Line Pitch #2
31:15
Unused
-
14: 3
PSU_PITCH2
R/W
Line pitch DMA #2, signed value (two’s complement)
used for planes 2 and 3
2:0
Unused
-
Offset 0x10 6350
Target Base Address #3
31:28
Unused
-
27: 3
PSU_BASE3
R/W
Base address DMA #3
used depending on PSU_BAMODE setting
2:0
PSU_OFFSET3
R/W
Base address byte offset plane 3
bits dene pixel offset within multi pixel 64 bit words
(e.g. a 16bit pixel can be placed on any 16 bit boundary)
Offset 0x10 6354
Target Base Address #4
31:28
Unused
-
27: 3
PSU_BASE4
R/W
Base address DMA #4
used depending on PSU_BAMODE setting
2: 0
Unused
-
Offset 0x10 6358
Target Base Address #5
31:28
Unused
-
27: 3
PSU_BASE5
R/W
Base address DMA #5
used depending on PSU_BAMODE setting
2: 0
Unused
-
Offset 0x10 635C
Target Base Address #6
31:28
Unused
-
27: 3
PSU_BASE6
R/W
Base address DMA #6
used depending on PSU_BAMODE setting
2: 0
Unused
-
Auxiliary Data Output Format Control Registers
Offset 0x10 6380
Auxiliary Capture Output Format
31:30
AUX_BAMODE
0
Base address mode
00 = pitch mode, wrap at end of buffer or window
01 = pitch mode, wrap at end of buffer
10 = append mode, wrap at end of buffer or window
11 = append mode, wrap at end of buffer
29:27
reserved
-
Table 10: Video Input Processor (VIP) 1 Registers …Continued
Bit
Symbol
Acces
s
Value
Description