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| 型號(hào)： | 935275672112 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8 I/O, PIA-GENERAL PURPOSE, PDSO20 |
| 封裝： | 4.40 MM, PLASTIC, MO-152, SOT-266-1, SSOP-20 |
| 文件頁數(shù)： | 32/33頁 |
| 文件大小： | 316K |
| 代理商： | 935275672112 |
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2002 Nov 22
8
Philips Semiconductors
Product specication
Remote 8-bit I/O expander for I2C-bus
PCF8574
6.4
Acknowledge
The number of data bytes transferred between the start
and the stop conditions from transmitter to receiver is not
limited. Each byte of eight bits is followed by one
acknowledge bit (see Fig.8). The acknowledge bit is a
HIGH level put on the bus by the transmitter whereas the
master generates an extra acknowledge related clock
pulse.
A slave receiver which is addressed must generate an
acknowledge after the reception of each byte. Also a
master must generate an acknowledge after the reception
of each byte that has been clocked out of the slave
transmitter. The device that acknowledges has to pull
down the SDA line during the acknowledge clock pulse, so
that the SDA line is stable LOW during the HIGH period of
the acknowledge related clock pulse, set-up and hold
times must be taken into account.
A master receiver must signal an end of data to the
transmitter by not generating an acknowledge on the last
byte that has been clocked out of the slave. In this event
the transmitter must leave the data line HIGH to enable the
master to generate a stop condition.
Fig.8 Acknowledgment on the I2C-bus.
handbook, full pagewidth
MBC602
S
START
condition
9
8
2
1
clock pulse for
acknowledgement
not acknowledge
acknowledge
DATA OUTPUT
BY TRANSMITTER
DATA OUTPUT
BY RECEIVER
SCL FROM
MASTER
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