- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄24773 > 935275581512 (NXP SEMICONDUCTORS) 8 I/O, PIA-GENERAL PURPOSE, PDSO16 PDF資料下載
參數(shù)資料
| 型號： | 935275581512 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8 I/O, PIA-GENERAL PURPOSE, PDSO16 |
| 封裝： | 7.50 MM, LEAD FREE, PLASTIC, MS-013, SOT-162-1, SO-16 |
| 文件頁數(shù)： | 4/33頁 |
| 文件大?。?/td> | 316K |
| 代理商： | 935275581512 |
第1頁第2頁第3頁當(dāng)前第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁
2002 Nov 22
12
Philips Semiconductors
Product specication
Remote 8-bit I/O expander for I2C-bus
PCF8574
7.2
Interrupt output
The PCF8574 provides an open-drain output (INT) which
can be fed to a corresponding input of the microcontroller
(see Figs 13 and 14). This gives these chips a type of
master function which can initiate an action elsewhere in
the system.
An interrupt is generated by any rising or falling edge of the
port inputs in the input mode. After time tiv the signal INT is
valid.
Resetting and reactivating the interrupt circuit is achieved
when data on the port is changed to the original setting or
data is read from or written to the port which has generated
the interrupt.
Resetting occurs as follows:
In the READ mode at the acknowledge bit after the rising
edge of the SCL signal
HIGH-to-LOW transition of the SCL signal
Interrupts which occur during the acknowledge clock
pulse may be lost (or very short) due to the resetting of
the interrupt during this pulse.
Each change of the I/Os after resetting will be detected
and, after the next rising clock edge, will be transmitted as
INT. Reading from or writing to another device does not
affect the interrupt circuit.
7.3
Quasi-bidirectional I/Os
A quasi-bidirectional I/O can be used as an input or output
without the use of a control signal for data direction
(see Fig.15). At power-on the I/Os are HIGH. In this mode
only a current source to VDD is active. An additional strong
pull-up to VDD allows fast rising edges into heavily loaded
outputs. These devices turn on when an output is written
HIGH, and are switched off by the negative edge of SCL.
The I/Os should be HIGH before being used as inputs.
handbook, full pagewidth
MBD976
MICROCONTROLLER
INT
PCF8574
(1)
PCF8574
(2)
V DD
INT
PCF8574
(16)
Fig.13 Application of multiple PCF8574s with interrupt.
Fig.14 Interrupt generated by a change of input to I/O P5.
handbook, full pagewidth
MBD972
S
0
1
0
A2
A1
A0
1
A
start condition
1
P5
R/W
acknowledge
from slave
1
SDA
SCL
DATA INTO
P5
t ir
INT
slave address (PCF8574)
data from port
1
234
567
8
P
stop
condition
t iv
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 935275672118 | 8 I/O, PIA-GENERAL PURPOSE, PDSO20 |
| 933851660112 | 8 I/O, PIA-GENERAL PURPOSE, PDSO16 |
| 935275581518 | 8 I/O, PIA-GENERAL PURPOSE, PDSO16 |
| 935271753118 | 8 I/O, PIA-GENERAL PURPOSE, PDSO20 |
| 935275581112 | 8 I/O, PIA-GENERAL PURPOSE, PDSO16 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 935277864112 | 制造商:NXP Semiconductors 功能描述:IC CPU |
| 935278818112 | 制造商:NXP Semiconductors 功能描述:LCD DRVR 20DIGIT 2.5V/3.3V/5V 56-Pin VSO Tube |
| 935280517132 | 制造商:NXP Semiconductors 功能描述:IC TRANSLATING BUFFER 6XSON |
| 935281751112 | 制造商:NXP Semiconductors 功能描述:IC BUFFER/DVR 16BIT 3ST 48TSSOP |
| 935281751118 | 制造商:NXP Semiconductors 功能描述:IC BUFFER/DVR 16BIT 3ST 48TSSOP |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。