
Philips Semiconductors
PNX15xx Series
Volume 1 of 1
Chapter 15: Audio Output
PNX15XX_SER_3
Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 3 — 17 March 2006
15-11
indicated for each operating mode. Note that for high sample rates with more than
four channels (96 kHz, 32-bit, >4ch), Audio Out cannot guarantee error-free operation
due to data bus latency restrictions.
2.9 Error Behavior
In normal operation, the system controller and Audio Out hardware continuously
exchange buffers without ever failing to transmit a sample. If the system controller
fails to provide a new DMA buffer address in time, the UNDERRUN error ag is raised
and the last valid sample or sample pair is repeated until a new buffer of data is
assigned by an ACK1 or ACK2. The UNDERRUN ag is
not affected by ACK1 or
ACK2; it can only be cleared by an explicit ACK_UDR.
Table 6: Audio Out Latency Tolerance Examples
Transfer Mode
Fs (kHz)
T (nSec)
* Max Latency (uSec)
(with T=1/Fs)
2 ch stereo
16 bit/sample
48.0
20833
354.17
4 ch stereo
16 bit/sample
48.0
20833
187.50
6 ch stereo
16 bit/sample
48.0
20833
104.17
8 ch stereo
16 bit/sample
48.0
20833
104.17
2 ch stereo
32 bit/sample
48.0
20833
187.50
4 ch stereo
32 bit/sample
48.0
20833
104.17
6 ch stereo
32 bit/sample
48.0
20833
62.50
8 ch stereo
32 bit/sample
48.0
20833
62.50
2 ch stereo
16 bit/sample
96.0
10417
177.08
4 ch stereo
16 bit/sample
96.0
10417
93.75
6 ch stereo
16 bit/sample
96.0
10417
52.08
8 ch stereo
16 bit/sample
96.0
10417
52.08
2 ch stereo
32 bit/sample
96.0
10417
93.75
4 ch stereo
32 bit/sample
96.0
10417
52.08
* Max Latency (uSec) (with T=1/Fs)
2ch 16it stereo: (17 * T)2ch 32bit stereo:(9 * T)
4ch 16bit stereo:(9 * T)4ch 32bit stereo:(5 * T)
6ch 16bit stereo: (5 * T)6ch 32bit stereo:(3 * T)
8ch 16bit stereo:(5 * T)8ch 32bit stereo:(3 * T)