參數(shù)資料
型號： 935273916518
廠商： NXP SEMICONDUCTORS
元件分類： 顏色信號轉(zhuǎn)換
英文描述： COLOR SIGNAL DECODER, PBGA156
封裝： 15 X 15 MM, 1.15 MM HEIGHT, LEAD FREE, PLASTIC, MS-034, SOT-472-1, BGA-156
文件頁數(shù)： 144/178頁
文件大小： 988K
代理商： 935273916518
2004 Jul 22
68
Philips Semiconductors
Product specication
Multistandard video decoder with adaptive
comb lter and component video input
SAA7118
8.7.2
SIGNALS ASCLK AND ALRCLK
Two binary divided signals ASCLK and ALRCLK are provided for slower serial digital audio signal transmission and for
channel-select. The frequencies of these signals are defined by the following parameters:
SDIV[5:0] 38H[5:0] according to the equation:
LRDIV[5:0] 39H[5:0] according to the equation:
See Table 23 for examples.
Table 23 Programming examples for ASCLK/ALRCLK clock generation
8.7.3
OTHER CONTROL SIGNALS
Further control signals are available to define reference clock edges and vertical references; see Table 24.
Table 24 Control signals for reference clock edges and vertical references
AMXCLK
(MHz)
ASCLK
(kHz)
SDIV
ALRCLK
(kHz)
LRDIV
DECIMAL
HEX
DECIMAL
HEX
12.288
1536
3
03
48
16
10
768
7
07
8
08
11.2896
1411.2
3
03
44.1
16
10
2822.4
1
01
32
10
8.192
1024
3
03
32
16
10
2048
1
01
32
10
SIGNAL
DESCRIPTION
APLL[3AH[3]]
Audio PLL mode
0 = PLL closed
1 = PLL open
AMVR[3AH[2]]
Audio Master clock Vertical Reference
0 = internal V
1 = external V
LRPH[3AH[1]]
ALRCLK phase
0 = invert ASCLK, ALRCLK edges triggered by falling edge of ASCLK
1 = don’t invert ASCLK, ALRCLK edges triggered by rising edge of ASCLK
SCPH[3AH[0]]
ASCLK phase
0 = invert AMXCLK, ASCLK edges triggered by falling edge of AMXCLK
1 = don’t invert AMXCLK, ASCLK edges triggered by rising edge of AMXCLK
f
ASCLK
f
AMXCLK
SDIV
1
+
() 2
×
--------------------------------------
=
SDIV[5:0]
f
AMXCLK
2f
ASCLK
--------------------
1
–
=
f
ALRCLK
f
ASCLK
LRDIV
2
×
---------------------------
=
LRDIV[5:0]
f
ASCLK
2f
ALRCLK
-----------------------
=
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