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參數(shù)資料
| 型號： | 935272706551 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | ADC |
| 英文描述： | 3-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQFP144 |
| 封裝： | 20 X 20 MM, 1.40 MM HEIGHT, PLASTIC, SOT-486-1, LQFP-144 |
| 文件頁數(shù)： | 28/61頁 |
| 文件大?。?/td> | 326K |
| 代理商： | 935272706551 |
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2004 May 18
34
Philips Semiconductors
Product specication
Triple 8-bit video ADC up to 270 Msps
TDA8754
9.15
Inverter register
Table 45 INVERTER (16h) bit allocation
Table 46 INVERTER (16h) bit description
4
CLPSEL1
can be used to select the clamp signal; see bit CLPSEL2
0 = PLL reference signal
1 = clamp input
3
CLPH
inhibits the clamp signal during the Vsynco or coast signal; see bit TSTCOAST (Table 42)
0 = clamp inhibited during Vsynco
1 = clamp active during Vsynco
2
CLPENL
denes if clamp input works on edge or on level
0 = on edge; for all frequencies (must be preferably chosen)
1 = on level; only for frequencies below 45 MHz to have proper clamp function
1
ICLP
dedicated for test mode; should be forced to logic 0
0
CLPT
denes if the test mode of the clamp is active
0 = not active
1 = active
BIT
7
6
543210
Symbol
COS
CLPS
CKREFO
INV
DEOINV
RGB
HSOINV
RGB
VSOINV
RGB
FIELDO
INV
Default
X
0
BIT
SYMBOL
DESCRIPTION
7
not used
6
COS
enables the COAST input signal to be inverted
0 = non-inverted
1 = inverted
5
CLPS
enables the CLAMP input signal to be inverted
0 = non-inverted
1 = inverted
4
CKREFOINV
enables the output CKREFO to be inverted
0 = non-inverted
1 = inverted
3
DEOINVRGB
enables the output DEO to be inverted
0 = non-inverted
1 = inverted
2
HSOINVRGB
enables the output HSYNCO to be inverted
0 = non-inverted
1 = inverted
BIT
SYMBOL
DESCRIPTION
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