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| 型號： | 935272704518 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | ADC |
| 英文描述： | 3-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQFP144 |
| 封裝： | 20 X 20 MM, 1.40 MM HEIGHT, PLASTIC, SOT-486-1, LQFP-144 |
| 文件頁數(shù)： | 27/61頁 |
| 文件大小： | 326K |
| 代理商： | 935272704518 |
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2004 May 18
33
Philips Semiconductors
Product specication
Triple 8-bit video ADC up to 270 Msps
TDA8754
9.13
Vertical sync selection register
Table 41 VSYNCSEL (14h) bit allocation
Table 42 VSYNCSEL (14h) bit description
9.14
Clamp register
Table 43 CLAMP (15h) bit allocation
Table 44 CLAMP (15h) bit description
BIT
76
543
21
0
Symbol
TSTCOAST
COE
VSS
COSSEL2
COSSEL1
Default
X
0
BIT
SYMBOL
DESCRIPTION
7 to 5
not used
4
TSTCOAST
switches a multiplexer to select the output signal on pin VSYNCO
0 = output of the separator function
1 = output of the coast function
3
COE
enables coast mode
0 = coast mode
1 = no coast mode
2
VSS
enables VSYNC input signal to be inverted
0 = non-inverted
1 = inverted
1
COSSEL2
selects signal for coast PLL mode
0 = signal selected with bit COSSEL1
1 = pin coast
0
COSSEL1
can be used for the coast PLL mode; see bit COSSEL2
0 = VSYNC input
1 = VSYNC from the sync separator
BIT
765
4321
0
Symbol
HSOSEL
CLPSEL2
CLPSEL1
CLPH
CLPENL
ICLP
CLPT
Default
X
0
1
0000
0
BIT
SYMBOL
DESCRIPTION
7
not used
6
HSOSEL
denes the signal on the output HSYNCO; see Section 8.3
0 = Hsync from the Hcounter
1 = Ckref is reference of the PLL
5
CLPSEL2
can be used to select the clamp signal
0 = Hsync signal generated by the pixel counter
1 = signal selected with bit CLPSEL1
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