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參數(shù)資料
| 型號： | 935270142118 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 模擬信號調(diào)理 |
| 英文描述： | SPECIALTY ANALOG CIRCUIT, PDSO16 |
| 封裝： | 3.90 MM, 0.635 MM PITCH, PLASTIC, SOT-519-1, SSOP-16 |
| 文件頁數(shù)： | 12/16頁 |
| 文件大?。?/td> | 136K |
| 代理商： | 935270142118 |
Philips Semiconductors
Product data
NE1618
Temperature monitor for microprocessor systems
2002 Jan 04
5
ELECTRICAL CHARACTERISTICS
VDD = 3.3 V; Tamb = 5 °C to +120 °C; unless otherwise noted.
PARAMETER
CONDITIONS
LIMITS
UNIT
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Temperature resolution
1
°C
Local temperature error
Tamb = +60 °C to +100 °C
VDD = 3.3 V
±0.75
±1.5
°C
VDD = 5.0 V 1
±1.25
±2.0
°C
Tamb = 0 °C to +120 °C
VDD = 3.3 V
±2.0
±3.0
°C
VDD = 5.0 V 1
±2.5
±3.5
°C
Remote temperature error
(1 Cl i
)
Tremote = +60 °C to +100 °C
VDD = 3.3 V
±3.0
°C
(1
°C resolution)
VDD = 5.0 V 1
±3.5
°C
Tremote = 0 °C to +120 °C
VDD = 3.3 V
±5.0
°C
VDD = 5.0 V 1
±5.5
°C
Extended Remote temp error
(0 12
Cl i
)
Tremote = +70 °C to +100 °C
VDD = 3.3 V
±1.0
°C
(0.125
°C resolution)
VDD = 5.0 V 1
±1.5
°C
Tremote = 0 °C to +120 °C
VDD = 3.3 V
±3.0
°C
VDD = 5.0 V 1
±3.5
°C
Extended relative temp error 2
(0 12
Cl i
)
Tremote = +70 °C to +100 °C
VDD = 3.3 V
±0.25
°C
(0.125
°C resolution)
VDD = 5.0 V 1
±0.75
°C
Tremote = 0 °C to +120 °C
VDD = 3.3 V
±0.50
°C
VDD = 5.0 V 1
±1.0
°C
Under voltage lockout 3
VDD input disables A/D conversion 4
2.1
2.95
V
Power-on reset threshold
VDD input falling edge 5
1.0
2.5
V
Power supply current (average)
Conversion data = 02h
80
160
A
Conversion data = 05h
100
270
A
Power supply current (standby)
SMBus inactive
3
10
A
Conversion time (busy duration)
Basic measurement
150
ms
Extended measurement
750
ms
Conversion rate error
Percentage error in programmed rate > 1 Hz 6
–30
+30
%
Remote sensor source current
HIGH level
100
A
LOW level
10
A
Address pin bias current
Momentary as the address is being read 7,8
50
A
NOTES:
1. The NE1618 is optimized for 3.3 VDD operation. The listed accuracy limits for 5 VDD operation are guaranteed by design and 100% QA
sample tested in production.
2. Guaranteed by design.
3. Definition of Under Voltage Lockout (UVL): The value of VDD below which the internal A/D converter is disabled. This is designed to be a
minimum of 200 mV above the power-on reset. During the time that it is disabled, the temperature that is in the “read temperature registers”
will remain at the value that it was before the A/D was disabled. This is done to eliminate the possibility of reading unexpected false
temperatures due to the A/D converter not working correctly due to low voltage. In case of power-up (rising VDD), the reading that is stored
in the “read temperature registers” will be the default value of 0
°C. VDD will rise to the value of UVL, at which point the A/D will function
correctly and normal temperatures will be read.
4. VDD (rising edge) voltage below which the ADC is disabled.
5. VDD (falling edge) voltage below which the logic is reset.
6. For conversion rate
≤ 1 Hz, extended measurement requires about 400 ms more for conversion.
7. Address is read at power-up and at start of conversion for all conversions except the fastest rate.
8. Due to the bias current, any pull-up/down resistors should be
≤ 2 k.
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