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參數(shù)資料
| 型號： | 935269775118 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 模擬信號調(diào)理 |
| 英文描述： | SPECIALTY ANALOG CIRCUIT, PDSO8 |
| 封裝： | 3.90 MM, PLASTIC, MS-012, SOT-96-1, SO-8 |
| 文件頁數(shù)： | 4/18頁 |
| 文件大?。?/td> | 161K |
| 代理商： | 935269775118 |
Philips Semiconductors
Product data
LM75A
Digital temperature sensor and thermal Watchdog
2001 Jul 16
12
Data communication
The communication between the host and the LM75A must strictly
follow the rules as defined by the I2C-bus management. The
protocols for LM75A register read/write operations are illustrated by
the Figures as follows with these definitions:
1. Before a communication, the I2C-bus must be free or not busy. It
means that the SCL and SDA lines must be both released by all
devices on the bus, and they become HIGH by the bus pull-up
resistors.
2. The host must provide SCL clock pulses necessary for the
communication. Data is transferred in sequence of 9 SCL clock
pulses for every 8-bit data byte followed by 1-bit status of the
acknowledgement.
3. During data transfer, except the Start and Stop signals, the SDA
signal must be stable while the SCL signal is HIGH. It means
that SDA signal can be changed only during the LOW duration
of the SCL line.
4. S: Start signal, initiated by the host to start a communication,
the SDA goes from HIGH-to-LOW while the SCL is HIGH.
5. RS: Re-start signal, same as the Start signal, to start a read
command that follows a write command.
6. P: Stop signal, generated by the host to stop a communication,
the SDA goes from LOW-to-HIGH while the SCL is HIGH. The
bus becomes free thereafter.
7. W: Write bit, when the Write/Read bit = LOW in a write
command.
8. R: Read bit, when the Write/Read bit = HIGH in a read
command.
9. A: Device Acknowledge bit, returned by the LM75A. It is LOW if
the device works properly and HIGH if not. The host must
release the SDA line during this period in order to give the
device the control on the SDA line.
10. A
′: Master Acknowledge bit, not returned by the device, but set
by the master or host in reading 2-byte data. During this clock
period, the host must set the SDA line to LOW in order to notice
the device that the first byte has been read for the device to
provide the second byte onto the bus.
11. NA: Not-Acknowledge bit. During this clock period, both the
device and host release the SDA line at the end of a data
transfer, the host is then enabled to generate the Stop signal.
12. In a write protocol, data is sent from the host to the device and
the host controls the SDA line, except during the clock period
when the device sends to the bus the device acknowledgement
signal.
13. In a read protocol, data is sent to the bus by the device and the
host must release the SDA line during the time that the device is
providing data onto the bus and controlling the SDA line, except
during the clock period when the master sends to the bus the
master acknowledgement signal.
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