參數(shù)資料
型號： 935269576557
廠商： NXP SEMICONDUCTORS
元件分類： 消費(fèi)家電
英文描述： SPECIALTY CONSUMER CIRCUIT, PQFP100
封裝： 14 X 14 MM, 1 MM HEIGHT, HEAT SINK, PLASTIC, SOT-638-1, TQFP-100
文件頁數(shù)： 37/84頁
文件大?。?/td> 1054K
代理商： 935269576557
Koninklijke Philips Electronics N.V. Copyright 2001. All rights reserved.
9397 750 08865
42 of 84
Rev. 02 — 8 October 2001
Product data
PNX8510/11
Philips Semiconductors
Analog Companion Chip
Offset 0x7F
DTTXL2
7:0
R/W
0x00
DTTXL
Individual lines in both fields (PAL counting) can be disabled for
insertion of teletext by the respective bits.
Disabled line = LINExx(50Hz field rate)
Bit 7 = Line 20; Bit 0 = Line 13
The mask is only effective if the lines are enabled via TTXOVS/
TTXOVE and TTXEVS/TTXEVE.
Offset 0x80
LCNT_ARRAY_LINE - Not present in secondary video channel.
7:0
R/W
-
LCNT_ARRAY_LINE
Line count array programming data lower 8 bits
Offset 0x81
LCNT_ARRAY_LINE - Not present in secondary video channel.
7:6
-
Unused
5:0
R/W
-
LCNT_ARRAY_LINE
Line count array programming data upper 6 bit
Offset 0x82
LCNT_ARRAY_ADR - Not present in secondary video channel.
7:4
-
Unused
3:0
R/W
-
LCNT_ARRAY_ADR
Line count array programming address
Writing to this address initiates the transfer of the data previously
written into locations 80 and 81 into an internal register array.
Offset 0x83—0x85
LTYPE_ARRAY_LINE - Not present in secondary video channel.
7:0
R/W
-
LTYPE_ARRAY_LINE
0x83 -> LSBs
0x85 -> MSBs
Line type array programming data
2:0 = first index
...
23:21 = last index
Offset 0x86
LTYPE_ARRAY_ADR - Not present in secondary video channel.
7:4
-
Unused
3:0
R/W
-
LTYPE_ARRAY_ADR
Line type array programming address
Writing to this address initiates the transfer of the data previously
written into locations 83 through 85 into an internal register array.
Offset 0x87—0x8D
LPATT_ARRAY_LINE - Not present in secondary video channel.
7:0
R/W
-
LPATT_ARRAY_LINE
0x87 -> LSBs
0x8D -> MSBs
Line pattern array programming data
13:4 = first duration 3:0 = first index
...
55:46 = last duration 45:42 last index
Offset 0x8E
LPATT_ARRAY_ADR - Not present in secondary video channel.
7:3
-
Unused
2:0
R/W
-
LTYPE_ARRAY_ADR
Line pattern array programming address
Writing to this address initiates the transfer of the data previously
written into locations 87 through 8D into an internal register array.
Offset 0x8F
must be initialized to zero.
Offset 0x90—0x94
GPIO5-GPIO1 (0x90=GPIO1, ..., 0x94=GPIO5) Not present in secondary video channel.
7
R/W
0
GPIO_IN_EN4
GPIO input enable 4
6
R/W
0
GPIO_IN_EN3
GPIO input enable 3
5
R/W
0
GPIO_IN_EN2
GPIO input enable 2
4
R/W
0
GPIO_IN_EN1
GPIO input enable 1
3
R/W
1
OEN
Output enable
2
R/W
0
STATUS
Write to register sets the GPIO pin if output select is set to 2’b11.
Read to register returns the status of the gpio pin if GPIO_IN_EN4
is set, otherwise it returns 0.
Bits
Read/
Write
Reset
Value
Name
(Field or Function)
Description
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