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參數(shù)資料
| 型號(hào)： | 935269568118 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16 I/O, PIA-GENERAL PURPOSE, PDSO24 |
| 封裝： | 5.30 MM, PLASTIC, MO-150, SOT-340-1, SSOP-24 |
| 文件頁數(shù)： | 14/17頁 |
| 文件大?。?/td> | 151K |
| 代理商： | 935269568118 |
Philips Semiconductors
Product data
PCA9555
16-bit I2C and SMBus I/O port with interrupt
2002 Jul 26
6
REGISTERS
Command Byte
Command
Register
0
Input port 0
1
Input port 1
2
Output port 0
3
Output port 1
4
Polarity inversion port 0
5
Polarity inversion port 1
6
Configuration port 0
7
Configuration port 1
The command byte is the first byte to follow the address byte during
a write transmission. It is used as a pointer to determine which of the
following registers will be written or read.
Registers 0 and 1 — Input Port Registers
This register is an input-only port. It reflects the incoming logic levels
of the pins, regardless of whether the pin is defined as an input or an
output by Register 3. Writes to this register have no effect.
Registers 2 and 3 — Output Port Registers
bit
O0.7
O0.6
O0.5
O0.4
O0.3
O0.2
O0.1
O0.0
default
1
bit
O1.7
O1.6
O1.5
O1.4
O1.3
O1.2
O1.1
O1.0
default
1
This register is an output-only port. It reflects the outgoing logic
levels of the pins defined as outputs by Register 6 and 7. Bit values
in this register have no effect on pins defined as inputs. In turn,
reads from this register reflect the value that is in the flip-flop
controlling the output selection, NOT the actual pin value.
Registers 4 and 5 — Polarity Inversion Registers
bit
N0.7
N0.6
N0.5
N0.4
N0.3
N0.2
N0.1
N0.0
default
0
bit
N1.7
N1.6
N1.5
N1.4
N1.3
N1.2
N1.1
N1.0
default
0
This register allows the user to invert the polarity of the Input Port
register data. If a bit in this register is set (written with ‘1’), the Input
Port data polarity is inverted. If a bit in this register is cleared (written
with a ‘0’), the Input Port data polarity is retained.
Registers 6 and 7 — Configuration Registers
bit
C0.7
C0.6
C0.5
C0.4
C0.3
C0.2
C0.1
C0.0
default
1
bit
C1.7
C1.6
C1.5
C1.4
C1.3
C1.2
C1.1
C1.0
default
1
This register configures the directions of the I/O pins. If a bit in this
register is set (written with ‘1’), the corresponding port pin is enabled
as an input with high impedance output driver. If a bit in this register
is cleared (written with ‘0’), the corresponding port pin is enabled as
an output. Note that there is a high value resistor tied to VDD at each
pin. At reset the device’s ports are inputs with a pull-up to VDD.
POWER-ON RESET
When power is applied to VDD, an internal power-on reset holds the
PCA9555 in a reset state until VDD has reached VPOR. At that point,
the reset condition is released and the PCA9555 registers and
SMBus state machine will initialize to their default states.
DEVICE ADDRESS
0
1
0
A2
A1
A0
slave address
su01441
fixed
programmable
R/W
Figure 5. PCA9555 address
BUS TRANSACTIONS
Writing to the port registers
Data is transmitted to the PCA9555 by sending the device address
and setting the least significant bit to a logic 0 (see Figure 5 for
device address). The command byte is sent after the address and
determines which register will receive the data following the
command byte.
The eight registers within the PCA9555 are configured to operate
as four register pairs. The four pairs are Input Ports, Output Ports,
Polarity Inversion Ports, and Configuration Ports. After sending data
to one register, the next data byte will be sent to the other register in
the pair (see Figures and ). For example, if the first byte is sent to
Output Port (register 3), then the next byte will be stored in Output
Port 0 (register 2). There is no limitation on the number of data bytes
sent in one write transmission. In this way, each 8-bit register may
be updated independently of the other registers.
Reading the port registers
In order to read data from the PCA9555, the bus master must first
send the PCA9555 address with the least significant bit set to a
logic 0 (see Figure 5 for device address). The command byte is sent
after the address and determines which register will be accessed.
After a restart, the device address is sent again but this time, the
least significant bit is set to a logic 1. Data from the register defined
by the command byte will then be sent by the PCA9555 (see
Figures 8 and 9). Data is clocked into the register on the falling edge
of the acknowledge clock pulse. After the first byte is read,
additional bytes may be read but the data will now reflect the
information in the other register in the pair. For example, if you read
Input Port 1, then the next byte read would be Input Port 0. There is
no limitation on the number of data bytes received in one read
transmission but the final byte received, the bus master must not
acknowledge the data.
Interrupt Output
The open-drain interrupt output is activated when one of the port
pins change state and the pin is configured as an input. The
interrupt is deactivated when the input returns to its previous state or
the input port register is read (see Figure 9). A pin configured as an
output cannot cause an interrupt. Since each 8-bit port is read
independently, the interrupt caused by Port 0 will not be cleared by a
read of Port 1 or the other way around.
Note that changing an I/O from an output to an input may cause a
false interrupt to occur if the state of the pin does not match the
contents of the Input Port register.
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