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參數(shù)資料
| 型號： | 935269202112 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8 I/O, PIA-GENERAL PURPOSE, PDSO16 |
| 封裝： | 4.40 MM, PLASTIC, MO-153, SOT-403-1, TSSOP-16 |
| 文件頁數(shù)： | 11/15頁 |
| 文件大?。?/td> | 140K |
| 代理商： | 935269202112 |
Philips Semiconductors
Product data
PCA9554/PCA9554A
8-bit I2C and SMBus I/O port with interrupt
2002 Jul 26
5
SIMPLIFIED SCHEMATIC OF I/O0 TO I/O7
WRITE PULSE
DATA FROM
SHIFT REGISTER
VDD
I/O0 TO I/O7
VSS
WRITE
CONFIGURATION
PULSE
D
CK
FF
Q
CK
Q
FF
D
CK
Q
FF
D
CK
Q
FF
INPUT PORT
REGISTER
POLARITY
INVERSION
REGISTER
OUTPUT
PORT
REGISTER
DATA FROM
SHIFT REGISTER
DATA FROM
SHIFT REGISTER
WRITE
POLARITY
PULSE
CONFIGURATION
REGISTER
OUTPUT PORT
REGISTER DATA
INPUT PORT
REGISTER DATA
POLARITY
REGISTER DATA
READ PULSE
SU01472
Q
TO INT
100 k
Q1
Q2
NOTE:
At Power-on Reset, all registers return to default values.
Figure 4. Simplified schematic of I/O0 to I/O7
I/O port
When an I/O is configured as an input, FETs Q1 and Q2 are off,
creating a high impedance input with a weak pull-up (100 k
typ.) to
VDD. The input voltage may be raised above VDD to a maximum of
5.5 V.
If the I/O is configured as an output, then either Q1 or Q2 is enabled,
depending on the state of the output port register. Care should be
exercised if an external voltage is applied to an I/O configured as an
output because of the low impedance paths that exist between the
pin and either VDD or VSS.
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| 935269193112 | 8 I/O, PIA-GENERAL PURPOSE, PDSO16 |
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| 935269202118 | 8 I/O, PIA-GENERAL PURPOSE, PDSO16 |
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