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參數(shù)資料
| 型號： | 935268676115 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 鎖存器 |
| 英文描述： | LVC/LCX/Z SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, INVERTED OUTPUT, PDSO5 |
| 封裝： | PLASTIC, SOT-353, 5 PIN |
| 文件頁數(shù)： | 15/16頁 |
| 文件大小： | 70K |
| 代理商： | 935268676115 |
2001 Apr 04
8
Philips Semiconductors
Product specication
Single D-type ip-op; positive-edge trigger
74LVC1G80
AC CHARACTERISTICS
GND = 0 V; tr =tf ≤ 2.0 ns; unless otherwise specied.
SYMBOL
PARAMETER
TEST CONDITIONS
Tamb (°C)
UNIT
WAVEFORMS
VCC (V)
40 to +85
MIN.
TYP.
MAX.
tPHL/tPLH
propagation delay CP to Q
see Figs 5 and 7
1.65 to 1.95
1.0
3.4
9.9
ns
2.3 to 2.7
0.5
2.3
7.0
ns
2.7
0.5
2.5
6.0
ns
3.0 to 3.6
0.5
2.4
5.2
ns
4.5 to 5.5
0.5
1.8
4.5
ns
tsu
set-up time D to CP
see Figs 6 and 7
1.65 to 1.95
3.0
0.8
ns
2.3 to 2.7
2.5
0.6
ns
2.7
2.5
0.5
ns
3.0 to 3.6
2.0
0.4
ns
4.5 to 5.5
2.0
0.5
ns
th
hold time D to CP
see Figs 6 and 7
1.65 to 1.95
0
0.6
ns
2.3 to 2.7
0
0.4
ns
2.7
0.5
0.2
ns
3.0 to 3.6
0.5
0.2
ns
4.5 to 5.5
0.5
0.1
ns
tW
clock pulse with HIGH or LOW see Figs 6 and 7
1.65 to 1.95
3.0
1.1
ns
2.3 to 2.7
2.5
0.7
ns
2.7
2.5
0.6
ns
3.0 to 3.6
2.5
0.6
ns
4.5 to 5.5
2.0
0.5
ns
fmax
maximum clock pulse
frequency
see Figs 6 and 7
1.65 to 1.95
100
300
MHz
2.3 to 2.7
150
350
MHz
2.7
150
300
MHz
3.0 to 3.6
150
450
MHz
4.5 to 5.5
200
500
MHz
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