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參數(shù)資料
| 型號： | 935268498557 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | PLL合成/DDS/VCOs |
| 英文描述： | PLL FREQUENCY SYNTHESIZER, 2500 MHz, PBCC24 |
| 封裝： | 4 X 4 MM, 0.65 MM HEIGHT, PLASTIC, HBCC-24 |
| 文件頁數(shù)： | 26/28頁 |
| 文件大?。?/td> | 278K |
| 代理商： | 935268498557 |
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Philips Semiconductors
Product data
SA8028
2.5 GHz sigma delta fractional-N /
760 MHz IF integer frequency synthesizers
2002 Feb 22
7
SYMBOL
UNIT
MAX.
TYP.
MIN.
CONDITIONS
PARAMETER
Phase noise (condition RSET = 7.5 k, CP = 00, non speed-up mode)
L(f)
Synthesizer’s contribution to close-in phase
noise of 900 MHz RF signal at 5 kHz offset.
fREF = 13 MHz, TCXO,
fCOMP = 13 MHz
indicative, not tested
–
–99
–
dBc/Hz
Synthesizer’s contribution to close-in phase
noise of 1800 MHz RF signal at 5 kHz offset.
As above
–
–93
–
dBc/Hz
Synthesizer’s contribution to close-in phase
noise of 800 MHz RF signal at 5 kHz offset.
fREF = 19.44/19.68 MHz, TCXO,
fCOMP = 19.44/19.68 MHz
indicative, not tested
–
–101
–
dBc/Hz
Synthesizer’s contribution to close-in phase
noise of 2100 MHz RF signal at 5 kHz offset.
As above
–
–93
–
dBc/Hz
Interface logic input signal levels
VIH
HIGH level input voltage
0.7*VDD
–
VDD+0.3
V
VIL
LOW level input voltage
–0.3
–
0.3*VDD
V
ILEAK
Input leakage current
VDD = 3 V, VIH = 3 V,
VIL = 0 V
–0.5
–
+0.5
A
Lock detect output signal (in push/pull mode) and Data output signal (in readout test mode)
VOL
LOW level output voltage
Isink = 2 mA
–
0.4
V
VOH
HIGH level output voltage
Isource = –2 mA
VDD–0.4
–
V
NOTES:
1.
SET
V
SET
R
ISET =
bias current for charge pumps.
2. The relative output current variation is defined as:
;
|
)
(
2
1
2
1
2
I
ZOUT
+
–
=
I
ZOUT
×
With I1 @ V1 = 0.6 V, I2 @V2 = VDDCP – 0.7 V (see Figure 3).
I2
I1
I2
I1
V1
V2
CURRENT
VPH
SR00602
IZOUT
VOLTAGE
Figure 3.
Relative output current variation.
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