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參數(shù)資料
| 型號： | 935268119118 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 模擬信號調(diào)理 |
| 英文描述： | SPECIALTY ANALOG CIRCUIT, PDSO16 |
| 封裝： | 3.90 MM, 0.635 MM PITCH, PLASTIC, SOT-519-1, SSOP-16 |
| 文件頁數(shù)： | 13/16頁 |
| 文件大?。?/td> | 128K |
| 代理商： | 935268119118 |
Philips Semiconductors
Product data
NE1617A
Temperature monitor for microprocessor systems
2001 Dec 14
6
SMBus INTERFACE AC SPECIFICATIONS
VDD = 3.0 V to 3.6 V; Tamb = 0 _C to +125 _C unless otherwise noted.
These specifications are guaranteed by design and not tested in production.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNIT
VIH
Logic input high voltage for STBY, SCLK, SDATA
VDD = 3 V to 5.5 V
2.2
V
VIL
Logic input low voltage for STBY, SCLK, SDATA
VDD = 3 V to 5.5 V
0.8
V
IOL
Logic output low sink current for
ALERT
SDATA
VOL = 0.4 V
VOL = 0.6 V
1.0
6.0
mA
IIH & IIL
Logic input current
VIN = VDD or GND
–1.0
1.0
A
CIN
SMBus input capacitance for SCLK,SDATA
5
pF
fSCLK
SCLK operating frequency
See Figure 4
0
100
kHz
tLOW
SCLK low time
See Figure 4
4.7
5.0
s
tHIGH
SCLK high time
See Figure 4
4.0
5.0
s
tBUF
SMBus free time.
Delay from SDA stop to SDA start
See Figure 4
4.7
s
tHD:STA
Hold time of start condition.
Delay from SDA start to first SCL H–L
See Figure 4
4.0
s
tHD:DAT
Hold time of data.
Delay from SCL H–L to SDA edges
See Figure 4
0
ns
tSU:DAT
Set-up time of data.
Delay from SDA edges to SCL L–H
See Figure 4
250
ns
tSU:STA
Set-up time of repeat start condition.
Delay from SCL L–H to restart SDA
See Figure 4
250
ns
tSU:STO
Set-up time of stop condition.
Delay from SCL L–H to SDA stop
See Figure 4
4.0
s
tF
Fall time of SCL and SDA
See Figure 4
1.0
s
tBUF
P
S
SCLK
SDATA
SL01204
tHD:STA
SP
tLOW
tR
tF
tHD:STA
tHD:DAT
tHIGH
tSU:DAT
tSU:STA
tSU:STO
Figure 4. Timing measurements.
NOTE:
The NE1617A does not include the SMBus timeout capability (tLOW:SEXT and tLOW:MEXT).
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