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參數(shù)資料
| 型號(hào)： | 935267995118 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 鎖存器 |
| 英文描述： | AHC SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PDSO20 |
| 封裝： | 4.40 MM, PLASTIC, MO-153, SOT-360-1, TSSOP-20 |
| 文件頁數(shù)： | 20/20頁 |
| 文件大小： | 93K |
| 代理商： | 935267995118 |
2000 Aug 15
9
Philips Semiconductors
Product specication
Octal D-type ip-op with data enable;
positive-edge trigger
74AHC377; 74AHCT377
AC CHARACTERISTICS
Type 74AHC377
GND = 0 V; tr =tf ≤ 3.0 ns.
SYMBOL
PARAMETER
TEST CONDITIONS
Tamb (°C)
UNIT
WAVEFORMS
CL
25
40 to +85 40 to +125
MIN. TYP. MAX. MIN. MAX. MIN. MAX.
VCC = 3.0 to 3.6 V; typical values at VCC = 3.3 V
tPHL/tPLH
propagation delay
CP to Qn
see Figs 6 and 8 15 pF
5.6
12.8
1.0
15.0
1.0
16.0
ns
fmax
maximum clock pulse
frequency
see Figs 6 and 8
80
125
70
70
MHz
tPHL/tPLH
propagation delay
CP to Qn
see Figs 6 and 8 50 pF
8.0
16.0
1.0
18.0
1.0
20.0
ns
tW
clock pulse width
HIGH or LOW
see Figs 6 and 8
5.0
5.0
5.0
ns
tsu
set-up time Dn to CP
see Figs 7 and 8
5.0
5.0
5.0
ns
set-up time E to CP
5.0
5.0
5.0
ns
th
hold time Dn to CP
1.5
1.5
1.5
ns
hold time E to CP
1.5
1.5
1.5
ns
fmax
maximum clock pulse
frequency
see Figs 6 and 8
50
75
45
45
MHz
VCC = 4.5 to 5.5 V; typical values at VCC = 5.0 V
tPHL/tPLH
propagation delay
CP to Qn
see Figs 6 and 8 15 pF
3.9
9.0
1.0
10.5
1.0
11.5
ns
fmax
maximum clock pulse
frequency
see Figs 6 and 8
125
175
110
110
MHz
tPHL/tPLH
propagation delay
CP to Qn
see Figs 6 and 8 50 pF
5.6
10.5
1.0
12.0
1.0
13.5
ns
tW
clock pulse width
HIGH or LOW
see Figs 6 and 8
5.0
5.0
5.0
ns
tsu
set-up time Dn to CP
see Figs 7 and 8
4.5
4.5
4.5
ns
tsu
set-up time E to CP
4.5
4.5
4.5
ns
th
hold time Dn to CP
2.0
2.0
2.0
ns
th
hold time E to CP
2.0
2.0
2.0
ns
fmax
maximum clock pulse
frequency
see Figs 6 and 8
85
120
75
75
MHz
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