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參數(shù)資料
| 型號： | 935267992112 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 鎖存器 |
| 英文描述： | AHCT/VHCT SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PDSO20 |
| 封裝： | 7.50 MM, PLASTIC, MS-013AC, SOT-163-1, SO-20 |
| 文件頁數(shù)： | 12/20頁 |
| 文件大?。?/td> | 93K |
| 代理商： | 935267992112 |
2000 Aug 15
2
Philips Semiconductors
Product specication
Octal D-type ip-op with data enable;
positive-edge trigger
74AHC377; 74AHCT377
FEATURES
ESD protection:
HBM EIA/JESD22-A114-A exceeds 2000 V
MM EIA/JESD22-A115-A exceeds 200 V
CDM EIA/JESD22-C101 exceeds 1000 V
Balanced propagation delays
All inputs have Schmitt-trigger actions
Inputs accept voltages higher than VCC
Ideal for addressable register applications
Data enable for address and data synchronization
Eight positive-edge triggered D-type flip-flops
See “273” for master reset version
See “373” for transparent latch version
See “374” for 3-state version
For AHC only: operates with CMOS input levels
For AHCT only: operates with TTL input levels
Specified from 40 to +85 and from 40 to +125 °C.
DESCRIPTION
The 74AHC/AHCT377 D-type flip-flops are high-speed
silicon-gate CMOS devices and are pin compatible with
low power Schottky TTL (LSTTL). They are specified in
compliance with JEDEC standard No. 7A.
The 74AHC/AHCT377 devices have eight edge-triggered,
D-type flip-flops with individual D inputs and Q outputs.
A common clock (CP) input loads all flip-flops
simultaneously when the data enable (E) is LOW. The
state of each D input, one set-up time before the
LOW-to-HIGH clock transition, is transferred to the
corresponding output (Qn) of the flip-flop.
The E input must be stable only one set-up time prior to the
LOW-to-HIGH transition for predictable operation.
QUICK REFERENCE DATA
GND = 0 V; Tamb =25 °C; tr =tf ≤ 3.0 ns.
Notes
1. CPD is used to determine the dynamic power dissipation (PD in W).
PD =CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
∑ (CL × VCC2 × fo) = sum of outputs;
CL = output load capacitance in pF;
VCC = supply voltage in Volts.
2. The condition is VI = GND to VCC.
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
AHC
AHCT
tPHL/tPLH
propagation delay;
CP to Qn
CL = 15 pF; VCC = 5 V
3.9
4.0
ns
fmax
maximum clock frequency
CL = 15 pF; VCC = 5 V
175
140
MHz
CI
input capacitance
VI =VCC or GND
3.0
pF
CPD
power dissipation
capacitance
CL = 50 pF; f = 1 MHz;
notes 1 and 2
20
23
pF
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