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參數(shù)資料
| 型號(hào)： | 935267941128 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 時(shí)鐘及定時(shí) |
| 英文描述： | PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32 |
| 封裝： | 7 X 7 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-358-1, LQFP-32 |
| 文件頁數(shù)： | 2/8頁 |
| 文件大?。?/td> | 62K |
| 代理商： | 935267941128 |
Philips Semiconductors
Product specification
PCK953
50–125 MHz PECL input/CMOS output
3.3 V PLL clock driver
2
2001 Feb 08
853–2222 25600
DESCRIPTION
The PCK953 is a 3.3 V compatible, PLL-based clock driver device
targeted for high performance clock tree designs. With output
frequencies of up to 125 MHz, and output skews of 100 ps, the
PCK953 is ideal for the most demanding clock tree designs. The
devices employ a fully differential PLL design to minimize
cycle-to-cycle and phase jitter.
The PCK953 has a differential LVPECL reference input, along with
an external feedback input. These features make the PCK953 ideal
for use as a zero delay, low skew fanout buffer. The device
performance has been tuned and optimized for zero delay
performance. The MR/OE input pin will reset the internal counters
and 3-State the output buffers when driven HIGH.
The PCK953 is fully 3.3 V compatible and requires no external loop
filter components. All control inputs accept LVCMOS or LVTTL
compatible levels, while the outputs provide LVCMOS levels with the
ability to drive terminated 50
transmission lines. For series
terminated 50
lines, each of the PCK953 outputs can drive two
traces, giving the device an effective fanout of 1:18. The device is
packaged in a 7
× 7 mm 32-lead LQFP package to provide the
optimum combination of board density and performance.
FEATURES
Fully integrated PLL
Output frequency up to 125 MHz in PLL mode
Outputs disable in high impedance
LQFP packaging
55 ps cycle-to-cycle jitter typical
9 mA quiescent current, I
CCA, typical
60 ps static phase offset typical
Less than 10 A quiescent current, l
CCO, typical
PIN CONFIGURATION
1
2
3
4
5
6
7
VCCA
FB_CLK
NC
GNDI
NC
8
PECL_CLK
24
23
22
21
20
19
18
Q1
VCCO
Q2
GNDO
Q3
Q4
VCCO
17 GNDO
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
PECL_CLK
MR/OE
Q7
GNDO
Q6
PLL_EN
GNDO
QFB
Q0
GNDO
V
CCO
V
CCO
Q5
V
CCO
VCO_SEL
BYP
ASS
SW00625
ORDERING INFORMATION
PACKAGES
TEMPERATURE RANGE
ORDER CODE
DRAWING NUMBER
plastic low profile quad flat
package; 32 leads
0 to +70
°C
PCK953BD
SOT358-1
LOGIC DIAGRAM
7
PHASE
DETECTOR
PECL_CLK
FB_CLK
VCO_SEL
BYPASS
MR/OE
PLL_EN
LPF
VCO
200–500 MHz
B2
B4
QFB
Q0:6
Q7
SW00624
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