參數(shù)資料
型號(hào)： 935267939112
廠商： NXP SEMICONDUCTORS
元件分類(lèi)： 網(wǎng)絡(luò)接口
英文描述： DATACOM, INTERFACE CIRCUIT, PDSO8
封裝： 3.90 MM, PLASTIC, SOT-96-1, MS-012, SO-8
文件頁(yè)數(shù)： 12/13頁(yè)
文件大?。?/td> 120K
代理商： 935267939112
Philips Semiconductors
Product data
AU5790
Single wire CAN transceiver
2001 May 18
8
SYMBOL
UNIT
MAX.
TYP.
MIN.
CONDITIONS
PARAMETER
Pin CANH (continued)
–ICANHH
Bus short circuit current in
high-speed mode
VCANH = –1 V,
TxD = 0 V; NSTB = 5 V; EN = 0 V;
8 V < VBAT < 16 V
50
190
mA
ICANLG
Bus leakage current at loss of
ground
(I_CAN_LG = I_CANH + I_RTH)
0 V < VBAT < 16 V;
see Figure 3 in the test circuits
section
–50
50
A
Tsd
Thermal shutdown
Note 2
155
190
°C
Thys
Thermal shutdown hysteresis
Note 2
5
15
°C
VT
Bus input threshold
5.8 V < VBAT < 27 V,
all modes except sleep mode
1.8
2.2
V
VTL
Bus input threshold, low battery
5.5 V < VBAT < 5.8 V,
all modes except sleep mode
1.5
2.2
V
VTS
Bus input threshold in sleep mode
NSTB = 0 V, EN = 0 V,
VBAT > 11.3 V
6.15
8.1
V
VTSL
Bus input threshold in sleep mode,
low battery
NSTB = 0 V, EN = 0 V,
5.5 V < VBAT < 11.3 V
VBAT – 4.3
VBAT – 3.25
V
Pin RTH
VRTH1
Voltage on switched ground pin
IRTH = 1 mA
0.1
V
VRTH2
Voltage on switched ground pin
IRTH = 6 mA
1
V
Pins NSTB, EN
Vih
High level input voltage
5.5 V < VBAT < 27 V
3
V
Vil
Low level input voltage
5.5 V < VBAT < 27 V
1
V
Ii
Input current
Vi = 1 V and Vi = 5 V
15
50
A
Pin TxD
Vitxd
TxD input threshold
5.5 V < VBAT < 27 V
1
3
V
–Iiltxd
TxD low level input current in
normal mode
NSTB = 5 V, EN = 5 V, VTxD = 0 V
50
180
A
–Iihtxd
TxD high level input current in
sleep mode
NSTB = 0 V, EN = 0 V, VTxD = 5 V
–5
10
A
Pin RxD
Volrxd
RxD low level output voltage
IRxD = 2.2 mA;
VCANH = 10 V, all modes
0.45
V
Iolrxd
RxD low level output current
VRxD = 5 V; VCANH = 10 V
3
35
mA
Iohrxd
RxD high level leakage
VRxD = 5 V; VCANH = 0 V,
all modes
–10
+10
A
NOTES:
1. Operation at battery voltages down to 5.3 volts is guaranteed by design. Operation higher than 18 volts (18 V < VBAT < 27 V) for up to two
minutes is permitted if the thermal design of the board prevents reaching the thermal protection temperature limit, Tsd, otherwise the device
will self protect. Typically these requirements will be encountered during jump start operation at Tamb 85 °C and VBAT < 27 V. Refer to the
“Thermal Characteristics” section of this data sheet, or application note AN2005 for guidance.
2. This parameter is characterized but not subject to production test.
相關(guān)PDF資料
PDF描述
051-0437-303
935267939118 DATACOM, INTERFACE CIRCUIT, PDSO8
935267940112 DATACOM, INTERFACE CIRCUIT, PDSO14
051-0111-303
935267940118 DATACOM, INTERFACE CIRCUIT, PDSO14
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