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參數(shù)資料
| 型號： | 935267286112 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | Buffer和線驅(qū)動 |
| 英文描述： | LINE TRANSCEIVER, PDSO16 |
| 封裝： | 4.40 MM, PLASTIC, MO-153, SOT-403-1, TSSOP-16 |
| 文件頁數(shù)： | 7/25頁 |
| 文件大?。?/td> | 594K |
| 代理商： | 935267286112 |
Philips Semiconductors
ISP1105/1106/1107
Advanced USB transceivers
Product data
Rev. 07 — 29 March 2002
15 of 25
9397 750 09529
Koninklijke Philips Electronics N.V. 2002. All rights reserved.
[1]
Test circuit: see Figure 12.
[2]
Characterized only, not tested. Limits guaranteed by design.
Receiver timings (full-speed and low-speed mode)
Differential receiver
tPLH(rcv)
propagation delay
LOW-to-HIGH; see Figure 8
--15
ns
tPHL(rcv)
(D
+,D to RCV)
HIGH-to-LOW; see Figure 8
--15
ns
Single-ended receiver
tPLH(se)
propagation delay
LOW-to-HIGH; see Figure 8
--18
ns
tPHL(se)
(D
+,D to VP, VM)
HIGH-to-LOW; see Figure 8
--18
ns
Table 16:
Dynamic characteristics: analog I/O pins (D
+, D)[1]…continued
VCC = 4.0 to 5.5 V or Vreg(3.3) = 3.0 to 3.6 V; VCC(I/O) = 1.65 to 3.6 V; VGND = 0 V; see Table 10 for valid voltage level
combinations; Tamb = 40 to +85 °C; unless otherwise specied.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Fig 6.
Rise and fall times.
Fig 7.
Timing of OE to D
+, D.
Fig 8.
Timing of D
+, D to RCV, VP, VM.
Fig 9.
Timing of VO/VPO, FSE0/VMO to D
+, D.
MGS963
VOL
tFR, tLR
tFF, tLF
VOH
90%
10%
90%
MGS966
VOL
VOH
tPZH
tPZL
tPHZ
tPLZ
VOH 0.3 V
VOL +0.3 V
VCRS
0.9 V
1.65 V
0 V
logic input
differential
data lines
MGS965
VOL
VOH
tPHL(rcv)
tPHL(se)
tPLH(rcv)
tPLH(se)
VCRS
0.9 V
2.0 V
0.8 V
logic output
differential
data lines
MGS964
VOL
VOH
tPHL(drv)
tPLH(drv)
VCRS
0.9 V
1.65 V
0 V
logic input
differential
data lines
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