參數(shù)資料
型號(hào)： 935265527551
廠(chǎng)商： NXP SEMICONDUCTORS
元件分類(lèi)： 微控制器/微處理器
英文描述： SPECIALTY MICROPROCESSOR CIRCUIT, PQFP64
封裝： PLASTIC, QFP-64
文件頁(yè)數(shù)： 6/55頁(yè)
文件大?。?/td> 387K
代理商： 935265527551
1999 May 10
14
Philips Semiconductors
Preliminary specication
Universal Serial Bus (USB) CODEC
UDA1325
Table 6
Selection of data transfer type
Data bits 7 to 2 represent a 6-bit device address, with bit 7 being the MSB and bit 2 the LSB. The address of the ADAC
is 000101 (bits 7 to 2). In the event that the ADAC receives a different address, it will deselect its microcontroller interface
logic.
DATA TRANSFER MODE
The selection preformed in the address mode remains active during subsequent data transfers, until the ADAC receives
a new address command. The data transfer mode is characterized by L3_MODE being HIGH and a burst of 8 pulses on
L3_CLK, accompanied by 8 data bits. All transfers are bitwise, i.e. they are based on groups of 8 bits. Data will be stored
in the ADAC after the eight bit of a byte has been received. The principle of a multibyte transfer is illustrated in the figure
below.
PROGRAMMING THE SOUND PROCESSING AND OTHER FEATURES
The sound processing and other feature values are stored in independent registers. The first selection of the registers is
achieved by the choice of data transfer type. This is performed in the address mode, bits 1 and 0 (see Table 6).
The second selection is performed by bit 7 and/or bit 6 of the data byte depending of the selected data transfer type.
Data transfer type ‘a(chǎn)udio feature registers’
When the data transfer type ‘a(chǎn)udio feature registers’ is selected 4 audio feature registers can be selected depending on
bits 7 and 6 of the data byte (see Table 7).
BIT1
BIT0
DATA TRANSFER TYPE
0
audio feature registers (volume left, volume right, bass and treble)
0
1
not used
1
0
control registers
1
not used
ndbook, full pagewidth
thalt
address
L3DATA
L3CLOCK
L3MODE
address
data byte #1
data byte #2
MGD018
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