參數(shù)資料
型號(hào)： 935265481112
廠商： NXP SEMICONDUCTORS
元件分類(lèi)： 門(mén)電路
英文描述： LVC/LCX/Z SERIES, HEX 1-INPUT NON-INVERT GATE, PDSO14
封裝： 3.90 MM, PLASTIC, MS-012, SOT-108-1, SO-14
文件頁(yè)數(shù)： 12/19頁(yè)
文件大小： 149K
代理商： 935265481112
2003 Feb 25
2
Philips Semiconductors
Product specication
Hex buffer with open-drain outputs
74LVC07A
FEATURES
5 V tolerant inputs and outputs (open drain) for
interfacing with 5 V logic
Wide supply voltage range from 1.65 to 5.5 V
CMOS low power consumption
Direct interface with TTL levels
Inputs accept voltages up to 5 V
Complies with JEDEC standard no. 8-1A
ESD protection:
HBM EIA/JESD22-A114-A exceeds 2000 V
MM EIA/JESD22-A115-A exceeds 200 V.
DESCRIPTION
The 74LVC07A is a high-performance, low-power,
low-voltage, Si-gate CMOS device, superior to most
advanced CMOS compatible TTL families. Inputs can be
driven from either 3.3 or 5 V devices. This feature allows
the use of these devices as translators in a mixed
3.3 to 5 V environment.
The 74LVC07A provides six non-inverting buffers.
The outputs of the 74LVC07A are open drain and can be
connected to other open-drain outputs to implement
active-LOW wired-OR or active-HIGH wired-AND
functions.
QUICK REFERENCE DATA
GND = 0 V; Tamb =25 °C; tr =tf ≤ 2.5 ns.
Note
1. CPD is used to determine the dynamic power dissipation (PD in W).
PD =CPD × VCC2 × fi × N+ Σ(CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in Volts;
N = total load switching outputs;
Σ(CL × VCC2 × fo) = sum of the outputs.
FUNCTION TABLE
See note 1.
Note
1. H = HIGH voltage level;
L = LOW voltage level;
Z = high-impedance OFF-state.
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
tPLZ/tPZL
propagation delay nA to nY
CL = 50 pF; VCC = 3.3 V
2.2
ns
CI
input capacitance
5.0
pF
CPD
power dissipation capacitance per gate
VI = GND to VCC; note 1
6.0
pF
INPUT
OUTPUT
nA
nY
LL
HZ
相關(guān)PDF資料
PDF描述
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08-50-0183 Crimp Socket Contact; Wire Size (AWG):26-22; Contact Material:Brass
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