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參數(shù)資料
| 型號： | 935265479118 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 門電路 |
| 英文描述： | LVC/LCX/Z SERIES, HEX 1-INPUT INVERT GATE, PDSO14 |
| 封裝： | 3.90 MM, PLASTIC, MS-012, SOT-108-1, SO-14 |
| 文件頁數(shù)： | 9/16頁 |
| 文件大小： | 71K |
| 代理商： | 935265479118 |
2000 Mar 07
2
Philips Semiconductors
Product specication
Hex inverter with open-drain outputs
74LVC06A
FEATURES
5 V tolerant inputs and outputs (open drain) for
interfacing with 5 V logic
Wide supply voltage range from 1.65 to 5.5 V
CMOS low power consumption
Direct interface with TTL levels
Inputs accept voltages up to 5 V
Complies with JEDEC standard no. 8-1A.
DESCRIPTION
The 74LVC06A is a high-performance, low-power,
low-voltage, Si-gate CMOS device, superior to most
advanced CMOS compatible TTL families.
Inputs can be driven from either 3.3 or 5 V devices. This
feature allows the use of these devices as translators in a
mixed 3.3 to 5 V environment.
The 74LVC06A provides six inverting buffers.
The outputs of the 74LVC06A devices are open drain and
can be connected to other open-drain outputs to
implement active-LOW wired-OR or active-HIGH
wired-AND functions.
QUICK REFERENCE DATA
GND = 0 V; Tamb =25 °C; tr =tf ≤ 2.5 ns.
Note
1. CPD is used to determine the dynamic power dissipation (PD in W).
PD =CPD × VCC2 × fi + Σ(CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in Volts;
Σ(CL × VCC2 × fo) = sum of the outputs.
FUNCTION TABLE
See note 1.
Note
1. H = HIGH voltage level;
L = LOW voltage level;
Z = high impedance OFF-state.
SYMBOL
PARAMETER
CONDITIONS
TYP.
UNIT
tPLZ/tPZL
propagation delay nA to nY
CL = 50 pF; VCC = 3.3 V
2.3
ns
CI
input capacitance
5.0
pF
CPD
power dissipation capacitance per gate
VI = GND to VCC; note 1
8.0
pF
INPUT
OUTPUT
nA
nY
LZ
HL
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