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參數(shù)資料
| 型號： | 935265474112 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 鎖存器 |
| 英文描述： | AHC SERIES, OCTAL LOW LEVEL TRIGGERED D LATCH, TRUE OUTPUT, PDSO16 |
| 封裝： | 4.40 MM, PLASTIC, MO-153, SOT-403-1, TSSOP-16 |
| 文件頁數(shù)： | 4/20頁 |
| 文件大?。?/td> | 95K |
| 代理商： | 935265474112 |
2000 Mar 14
12
Philips Semiconductors
Product specication
8-bit addressable latch
74AHC259;
74AHCT259
Type 74AHCT259
GND = 0 V; tr =tf ≤ 3.0 ns.
Note
1. Typical values at VCC = 5.0 V.
SYMBOL
PARAMETER
TEST CONDITIONS
Tamb (°C)
UNIT
WAVEFORMS
CL
25
40 to +85
40 to +125
MIN.
TYP.
MAX.
MIN.
MAX.
MIN.
MAX.
VCC = 4.5 to 5.5 V; note 1
tPHL/tPLH
propagation delay
DtoQn
see Figs 5 and 11
15 pF
4.1
7.5
1.0
9.0
1.0
10.0
ns
propagation delay
An to Qn
see Figs 6 and 11
5.5
9.5
1.0
11.5
1.0
12.5
ns
propagation delay
LE to Qn
see Figs 7 and 11
4.3
8.0
1.0
9.5
1.0
10.4
ns
tPHL
propagation delay
MR to Qn
see Figs 8 and 11
3.9
7.0
1.0
8.5
1.0
9.5
ns
tPHL/tPLH
propagation delay
DtoQn
see Figs 5 and 11
50 pF
5.4
9.5
1.0
11.0
1.0
12.0
ns
propagation delay
An to Qn
see Figs 6 and 11
6.6
12.0
1.0
14.0
1.0
15.5
ns
propagation delay
LE to Qn
see Figs 7 and 11
5.5
10.0
1.0
12.0
1.0
13.0
ns
tPHL
propagation delay
MR to Qn
see Figs 8 and 11
5.1
9.0
1.0
10.5
1.0
11.5
ns
tW
LE pulse width
HIGH or LOW
see Figs 7 and 11
5.0
5.0
5.0
ns
MR pulse width
LOW
see Figs 8 and 11
5.0
5.0
5.0
ns
tsu
set-up time
Dto LE, An to LE
see Figs 9,
10 and 11
4.0
4.0
4.0
ns
th
hold time D to LE,
An to LE
see Figs 9 and 11
1.0
1.0
1.0
ns
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