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參數(shù)資料
| 型號(hào)： | 935265473118 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 鎖存器 |
| 英文描述： | AHC SERIES, OCTAL LOW LEVEL TRIGGERED D LATCH, TRUE OUTPUT, PDSO16 |
| 封裝： | 3.90 MM, PLASTIC, MS-012, SOT-109-1, SO-16 |
| 文件頁(yè)數(shù)： | 5/20頁(yè) |
| 文件大小： | 95K |
| 代理商： | 935265473118 |
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2000 Mar 14
13
Philips Semiconductors
Product specication
8-bit addressable latch
74AHC259;
74AHCT259
AC WAVEFORMS
handbook, halfpage
MNA569
D input
Qn output
tPHL
tPLH
GND
VCC
VM
(2)
VM
(1)
VOH
VOL
Fig.5
The data input (D) to output (Qn)
propagation delays.
FAMILY
VI INPUT
REQUIREMENTS
VM(1)
INPUT
VM(2)
OUTPUT
AHC
GND to VCC
50% VCC 50% VCC
AHCT
GND to 3.0 V
1.5 V
50% VCC
handbook, halfpage
MNA568
An input
Qn output
tPHL
tPLH
GND
VCC
VM
(2)
VM
(1)
VOH
VOL
Fig.6
The address input (An) to output (Qn)
propagation delays.
FAMILY
VI INPUT
REQUIREMENTS
VM(1)
INPUT
VM(2)
OUTPUT
AHC
GND to VCC
50% VCC 50% VCC
AHCT
GND to 3.0 V
1.5 V
50% VCC
FAMILY
VI INPUT
REQUIREMENTS
VM(1)
INPUT
VM(2)
OUTPUT
AHC
GND to VCC
50% VCC 50% VCC
AHCT
GND to 3.0 V
1.5 V
50% VCC
Fig.7 The enable input (LE) to output (Qn) propagation delays, the enable input pulse width.
handbook, full pagewidth
MNA570
LE input
Qn output
tPHL
tPLH
tW
VM
(2)
VOH
VCC
GND
VCC
GND
VOL
VM
(1)
D input
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