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參數(shù)資料
| 型號： | 935265472118 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 鎖存器 |
| 英文描述： | AHCT/VHCT SERIES, OCTAL LOW LEVEL TRIGGERED D LATCH, TRUE OUTPUT, PDSO16 |
| 封裝： | 4.40 MM, PLASTIC, MO-153, SOT-403-1, TSSOP-16 |
| 文件頁數(shù)： | 2/20頁 |
| 文件大?。?/td> | 95K |
| 代理商： | 935265472118 |
2000 Mar 14
10
Philips Semiconductors
Product specication
8-bit addressable latch
74AHC259;
74AHCT259
AC CHARACTERISTICS
Type 74AHC259
GND = 0 V; tr =tf ≤ 3.0 ns.
SYMBOL
PARAMETER
TEST CONDITIONS
Tamb (°C)
UNIT
WAVEFORMS
CL
25
40 to +85
40 to +125
MIN.
TYP.
MAX.
MIN.
MAX.
MIN.
MAX.
VCC = 3.0 to 3.6 V; note 1
tPHL/tPLH
propagation delay
DtoQn
see Figs 5 and 11 15 pF
5.8
11.5
1.0
13.5
1.0
15.0
ns
propagation delay
An to Qn
see Figs 6 and 11
7.5
14.5
1.0
17.0
1.0
18.5
ns
propagation delay
LE to Qn
see Figs 7 and 11
6.2
12.0
1.0
14.0
1.0
15.2
ns
tPHL
propagation delay
MR to Qn
see Figs 8 and 11
5.4
10.5
1.0
12.5
1.0
13.5
ns
tPHL/tPLH
propagation delay
DtoQn
see Figs 5 and 11 50 pF
7.3
14.5
1.0
17.0
1.0
18.5
ns
propagation delay
An to Qn
see Figs 6 and 11
9.1
18.0
1.0
21.0
1.0
23.0
ns
propagation delay
LE to Qn
see Figs 7 and 11
7.7
15.5
1.0
17.5
1.0
19.0
ns
tPHL
propagation delay
MR to Qn
see Figs 8 and 11
7.0
13.5
1.0
15.5
1.0
17.0
ns
tW
LE pulse width
HIGH or LOW
see Figs 7 and 11
5.0
5.0
5.0
ns
MR pulse width
LOW
see Figs 8 and 11
5.0
5.0
5.0
ns
tsu
set-up time
Dto LE, An to LE
see Figs 9,
10 and 11
4.0
4.0
4.0
ns
th
hold time D to LE,
An to LE
see Figs 9 and 11
1.0
1.0
1.0
ns
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