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參數(shù)資料
| 型號： | 935265471118 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 鎖存器 |
| 英文描述： | AHCT/VHCT SERIES, OCTAL LOW LEVEL TRIGGERED D LATCH, TRUE OUTPUT, PDSO16 |
| 封裝： | 3.90 MM, PLASTIC, MS-012, SOT-109-1, SO-16 |
| 文件頁數(shù)： | 6/20頁 |
| 文件大?。?/td> | 95K |
| 代理商： | 935265471118 |
2000 Mar 14
14
Philips Semiconductors
Product specication
8-bit addressable latch
74AHC259; 74AHCT259
handbook, halfpage
MNA548
MR input
Qn output
tPHL
tW
VM
(2)
VOH
VCC
GND
VOL
VM
(1)
Fig.8
The conditional reset input (MR) to output
(Qn) propagation delays.
FAMILY
VI INPUT
REQUIREMENTS
VM(1)
INPUT
VM(2)
OUTPUT
AHC
GND to VCC
50% VCC 50% VCC
AHCT
GND to 3.0 V
1.5 V
50% VCC
handbook, halfpage
MNA550
An input
LE input
tsu
th
GND
ADDRESS STABLE
VCC
VM
(1)
VM
(1)
VCC
GND
Fig.9
The address set-up and hold time for
An inputs to LE input.
FAMILY
VI INPUT
REQUIREMENTS
VM(1)
INPUT
AHC
GND to VCC
50% VCC
AHCT
GND to 3.0 V
1.5 V
The shaded areas indicate when the input is permitted to change for
predictable output performance.
Fig.10 The data set-up and hold time for D input to LE input.
FAMILY
VI INPUT
REQUIREMENTS
VM(1)
INPUT
VM(2)
OUTPUT
AHC
GND to VCC
50% VCC 50% VCC
AHCT
GND to 3.0 V
1.5 V
50% VCC
The shaded areas indicate when the input is permitted to change
for predictable output performance.
handbook, full pagewidth
MNA549
GND
th
tsu
th
tsu
VM
(1)
VM
(1)
VM
(2)
VCC
VOH
VOL
VCC
Qn output
LE input
D input
Q = D
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