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參數(shù)資料
| 型號(hào)： | 935265441118 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, FLASH, 33 MHz, MICROCONTROLLER, PQCC44 |
| 封裝： | PLASTIC, LCC-44 |
| 文件頁數(shù)： | 26/52頁 |
| 文件大?。?/td> | 288K |
| 代理商： | 935265441118 |
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Philips Semiconductors
Preliminary data
P89C51RB2/P89C51RC2/
P89C51RD2
80C51 8-bit Flash microcontroller family
16KB/32KB/64KB ISP/IAP Flash with 512B/512B/1KB RAM
2001 Jun 27
32
DC ELECTRICAL CHARACTERISTICS
Tamb = 0°C to +70°C; VCC = 5 V ± 10% or –40°C to +85°C; 5 V ±5%; VSS = 0 V
SYMBOL
PARAMETER
TEST
LIMITS
UNIT
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP1
MAX
UNIT
VIL
Input low voltage
4.5 V < VCC < 5.5 V
–0.5
0.2VCC–0.1
V
VIH
Input high voltage (ports 0, 1, 2, 3, EA)
0.2VCC+0.9
VCC+0.5
V
VIH1
Input high voltage, XTAL1, RST
0.7VCC
VCC+0.5
V
VOL
Output low voltage, ports 1, 2, 38
VCC = 4.5 V
IOL = 1.6 mA2
0.4
V
VOL1
Output low voltage, port 0, ALE, PSEN 7, 8
VCC = 4.5 V
IOL = 3.2 mA2
0.45
V
VOH
Output high voltage, ports 1, 2, 3 3
VCC = 4.5 V
IOH = –30 A
VCC – 0.7
V
VOH1
Output high voltage (port 0 in external bus mode),
ALE9, PSEN3
VCC = 4.5 V
IOH = –3.2 mA
VCC – 0.7
V
IIL
Logical 0 input current, ports 1, 2, 3
VIN = 0.4 V
–1
–75
A
ITL
Logical 1-to-0 transition current, ports 1, 2, 36
VIN = 2.0 V
See Note 4
–650
A
ILI
Input leakage current, port 0
0.45 < VIN < VCC – 0.3
±10
A
ICC
Power supply current (see Figure 36):
See Note 5
Active mode (see Note 5)
Idle mode (see Note 5)
Power-down mode or clock stopped (see
Fi
42 f
diti
)
Tamb = 0°C to 70°C
<1
40
A
Figure 42 for conditions)
Tamb = –40°C to +85°C
50
A
Programming and erase mode
fosc = 20 MHz
60
mA
RRST
Internal reset pull-down resistor
40
225
k
CIO
Pin capacitance10 (except EA)
15
pF
NOTES:
1. Typical ratings are not guaranteed. The values listed are at room temperature, 5 V.
2. Capacitive loading on ports 0 and 2 may cause spurious noise to be superimposed on the VOLs of ALE and ports 1 and 3. The noise is due
to external bus capacitance discharging into the port 0 and port 2 pins when these pins make 1-to-0 transitions during bus operations. In the
worst cases (capacitive loading > 100 pF), the noise pulse on the ALE pin may exceed 0.8 V. In such cases, it may be desirable to qualify
ALE with a Schmitt Trigger, or use an address latch with a Schmitt Trigger STROBE input. IOL can exceed these conditions provided that no
single output sinks more than 5 mA and no more than two outputs exceed the test conditions.
3. Capacitive loading on ports 0 and 2 may cause the VOH on ALE and PSEN to momentarily fall below the VCC–0.7 specification when the
address bits are stabilizing.
4. Pins of ports 1, 2 and 3 source a transition current when they are being externally driven from 1 to 0. The transition current reaches its
maximum value when VIN is approximately 2 V.
5. See Figures 39 through 42 for ICC test conditions and Figure 36 for ICC vs Freq.
Active mode:
ICC(MAX) = (2.8 × FREQ. + 8)mA for all devices, in 6 clock mode; (1.4 × FREQ. + 8)mA in 12 clock mode.
Idle mode:
ICC(MAX) = (1.2 × FREQ. +1.0)mA in 6 clock mode; (0.6 × FREQ. +1.0)mA in 12 clock mode.
6. This value applies to Tamb = 0°C to +70°C.
7. Load capacitance for port 0, ALE, and PSEN = 100 pF, load capacitance for all other outputs = 80 pF.
8. Under steady state (non-transient) conditions, IOL must be externally limited as follows:
Maximum IOL per port pin:
15 mA (*NOTE: This is 85
°C specification.)
Maximum IOL per 8-bit port:
26 mA
Maximum total IOL for all outputs:
71 mA
If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed
test conditions.
9. ALE is tested to VOH1, except when ALE is off then VOH is the voltage specification.
10. Pin capacitance is characterized but not tested. Pin capacitance is less than 25 pF. Pin capacitance of ceramic package is less than 15 pF
(except EA is 25 pF).
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