參數(shù)資料
型號(hào)： 935264535557
廠商： NXP SEMICONDUCTORS
元件分類： 通信及網(wǎng)絡(luò)
英文描述： SPECIALTY TELECOM CIRCUIT, PQFP208
封裝： SOT-316, MQFP-208
文件頁(yè)數(shù)： 5/23頁(yè)
文件大?。?/td> 194K
代理商： 935264535557
1999 Jul 01
13
Philips Semiconductors
Product specication
Single Chip DAVIC/DVB-RC Cable Modem
VES1848
SYMBOL
PIN NUMBER
TYPE
DESCRIPTION
RESET
75
I
The RESET input is asynchronous, active low, and clears the VES
1848. When RESET goes low, the circuit immediately enters its
reset mode and normal operation will resume 4 OOB_clk falling
edges or 8 US_clk falling edges or 4 IBclk falling edges (depending
which delay is the bigger) later after RESET returned high. The
register contents are all initialized to their default values. The
minimum width of RESET at low level is the maximum of 4 OOB_clk
clock periods, 8 US_clk clock periods and 4 IBclk clock periods.
Fmicro
37
I
Controls the working frequency of the interface block.
If Fsysus > 65MHz then Fmicro must be set to Vdd.
If Fsysus
≤ 65MHz then Fmicro must be set to Vss.
nb_micro
36
I
If a single micro-processor is used to read the MAC data and the
application layers data then nb_micro must be set to Vdd.
If the application layers data are read by an other circuit then
nb_micro must be set to Vss.
utopia
33
I
Must be set to Vss.
Application layers data can only be read through a micro processor
interface.
AddM[7:0]
9,10,11,12
13,16,17,18
I
MAC interface address bus.
AddM[7] is the MSB.
DataM[7:0]
19,20,21,22
23,26,27,28
I/O
(5V)
MAC interface data bus.
DataM[7] is the MSB.
IntM
6
O
(5V)
MAC interface active low interrupt line.
IntM is an open drain output and therefore requires an external pull
up resistor to VCC.
hstbmodeM
32
I
Host interface STRobe mode (Intel=0, Motorola=1) for the MAC
interface.
hmuxmodeM
31
I
Host interface MUX mode for the MAC interface : address and data
multiplexed (=1) or not (=0).
rdn_enaM
8
I
MAC interface active low read strobe (Intel mode) or active low data
valid (Motorola mode).
wrnM
7
I
MAC interface active low write strobe (Intel mode) or
read(=1) /write(=0) qualifier (Motorola mode).
csM
29
I
MAC interface active low Chip Select.
aleM
30
I
MAC interface Address Latch Enable (only for multiplexed micro-
processor).
addA[4:0]
189,190,191
192,193
I
Application layers interface address bus.
addA[4] is the MSB.
dataA[15:0]
194,195,196,197
198,199,200,201
202,203,204,205
206,207,208,1
I/O
(5V)
Application layers interface data bus.
dataA[15] is the MSB.
IntA
182
O
(5V)
Application layers interface active low interrupt line.
IntA is an open drain output and therefore requires an external pull
up resistor to VCC.
hstbmodeA
3
I
Host interface STRobe mode (Intel=0, Motorola=1) for the
application layers interface.
hmuxmodeA
2
I
Host interface MUX mode for the application layers interface :
address and data multiplexed (=1) or not (=0).
rdn_enaA
184
I
application layers interface active low read strobe (Intel mode) or
active low data valid (Motorola mode).
wrnA
183
I
application layers interface active low write strobe (Intel mode) or
read(=1) /write(=0) qualifier (Motorola mode).
csA
186
I
application layers interface active low Chip Select.
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