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參數(shù)資料
| 型號： | 935264404112 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 時鐘及定時 |
| 英文描述： | PLL BASED CLOCK DRIVER, 9 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO24 |
| 封裝： | 4.40 MM, PLASTIC, MO-153, SOT-355-1, TSSOP-24 |
| 文件頁數(shù)： | 7/10頁 |
| 文件大?。?/td> | 79K |
| 代理商： | 935264404112 |
Philips Semiconductors
Product specification
PCK2509S
50–150 MHz 1:9 SDRAM clock driver
2001 Feb 02
6
TIMING REQUIREMENTS
Over recommended ranges of supply voltage and operating free-air temperature.
SYMBOL
PARAMETER
MIN
MAX
UNIT
fCLK
Clock frequency
50
150
MHz
Input clock duty cycle
40
60
%
Stabilization time1
1
ms
NOTE:
1. Time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal. For phase lock to be obtained,
a fixed-frequency, fixed-phase reference signal must be present at CLK. Until phase lock is obtained, the specifications for propagation
delay, skew, and jitter parameters given in the switching characteristics table are not applicable.
SWITCHING CHARACTERISTICS
Over recommended ranges of supply voltage and operating free-air temperature, CL = 30 pF
PARAMETER
FROM
TO
VCC, AVCC = 3.3 V ±0.3 V
UNIT
PARAMETER
(INPUT)/CONDITION
(OUTPUT)
MIN
TYP
MAX
UNIT
t
2
CLKIN
↑ = 100 MHz to 133 MHz
FBIN
↑
–100
100
ps
tphase error 2
CLKIN
↑ = 66 MHz
FBIN
↑
–125
125
ps
tphase error, – jitter 1, 3
CLKIN
↑ = 100 MHz to 133 MHz
FBIN
↑
–50
50
ps
tSK(0) 4
Any Y or FBOUT
200
ps
jitter(peak-peak)
CLKIN = 66 MHz to 133 MHz
Any Y or FBOUT
–80
80
ps
jitter (cycle-cycle) 1
CLKIN = 66 MHz to 133 MHz
Any Y or FBOUT
|65|
ps
Duty cycle reference 1
F(CLKIN
> 60 MHz)
Any Y or FBOUT
47
53
%
tr 1
VO = 0.4 to 2 V
Any Y or FBOUT
2.5
1
V/ns
tf 1
VO = 0.4 to 2 V
Any Y or FBOUT
2.5
1
V/ns
NOTES:
1. These parameters are not production tested.
2. This is considered as static phase offset.
3. Phase error does not include jitter. (tphase error = static tphase error – jitter (cycle-cycle)).
4. The tSK(0) specification is only valid for outputs with equal loading.
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