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參數(shù)資料
| 型號(hào)： | 935264009118 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 總線收發(fā)器 |
| 英文描述： | 18 1-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO56 |
| 封裝： | PLASTIC, TSSOP-56 |
| 文件頁(yè)數(shù)： | 5/12頁(yè) |
| 文件大?。?/td> | 95K |
| 代理商： | 935264009118 |
Philips Semiconductors
Product specification
GTL16612
18-bit GTL/GTL+ to LVTTL/TTL bidirectional
universal translator (3-State)
2
2000 Jun 19
853–2166 23903
FEATURES
18-bit bidirectional bus interface
Translates between GTL/GTL+ logic levels (B ports) and
LVTTL/TTL logic levels (A ports)
5 V I/O tolerant on the LVTTL/TTL side (A ports)
No bus current loading when LVTTL/TTL output is tied to 5 V bus
3-State buffers
Output capability: +64 mA/-32 mA on the LVTTL/TTL side
(A ports); +40 mA on the GTL/GTL+ side (B ports)
TTL input levels on control pins
Power-up reset
Power-up 3-State
Positive edge triggered clock inputs
Latch-up protection exceeds 500 mA per JESD78
ESD protection exceeds 2000 V HBM per JESD22-A114,
200 V MM per JESD22-A115 and 1000 V CDM per JESD22-C101
DESCRIPTION
The GTL16612 is a high-performance BiCMOS product designed for
VCC operation at 3.3 V with I/O compatibility up to 5 V.
This device is an 18-bit universal transceiver featuring non-inverting
3-State bus compatible outputs in both send and receive directions.
Data flow in each direction is controlled by output enable (OEAB and
OEBA), latch enable (LEAB and LEBA), and clock (CPAB and
CPBA) inputs. For A-to-B data flow, the device operates in the
transparent mode when LEAB is High. When LEAB is Low, the A
data is latched if CPAB is held at a High or Low logic level. If LEAB
is Low, the A-bus data is stored in the latch/flip-flop on the
Low-to-High transition of CPAB. When OEAB is Low, the outputs are
active. When OEAB is High, the outputs are in the high-impedance
state. The clocks can be controlled with the clock-enable inputs
(CEBA/CEAB).
Data flow for B-to-A is similar to that of A-to-B but uses OEBA,
LEBA and CPBA.
QUICK REFERENCE DATA
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
SYMBOL
PARAMETER
Tamb = 25°C
3.3 V
UNIT
tPLH
tPHL
Propagation delay
An to Bn or Bn to An
CL = 50 pF
1.9
ns
CIN
Input capacitance (Control pins)
VI = 0 V or VCC
4
pF
CI/O
I/O pin capacitance
Outputs disabled; VI/O = 0 V or VCC
8
pF
ICCZ
Total supply current
Outputs disabled
12
mA
ORDERING INFORMATION
PACKAGES
TEMPERATURE RANGE
ORDER CODE
DWG NUMBER
56-Pin Plastic TSSOP Type II
–40
°C to +85°C
GTL16612 DGG
SOT364-1
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