- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄24788 > 935263925005 (NXP SEMICONDUCTORS) LIQUID CRYSTAL DISPLAY DRIVER, UUC56 PDF資料下載
參數(shù)資料
| 型號： | 935263925005 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 顯示驅(qū)動器 |
| 英文描述： | LIQUID CRYSTAL DISPLAY DRIVER, UUC56 |
| 封裝： | DIE-56 |
| 文件頁數(shù)： | 7/46頁 |
| 文件大?。?/td> | 246K |
| 代理商： | 935263925005 |
第1頁第2頁第3頁第4頁第5頁第6頁當(dāng)前第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁
1998 Jul 30
15
Philips Semiconductors
Product specication
Universal LCD driver for low multiplex
rates
PCF8576C
6.5
Oscillator
6.5.1
INTERNAL CLOCK
The internal logic and the LCD drive signals of the
PCF8576C are timed either by the built-in oscillator or from
an external clock. When the internal oscillator is used,
OSC (pin 6) should be connected to VSS (pin 11). In this
event, the output from CLK (pin 4) provides the clock
signal for cascaded PCF8566s or PCF8576Cs in the
system.
Note that the PCF8576C is backwards compatible with the
PCF8576. Where resistor Rosc to VSS is present, the
internal oscillator is selected.
6.5.2
EXTERNAL CLOCK
The condition for external clock is made by tying OSC
(pin 6) to VDD; CLK (pin 4) then becomes the external
clock input.
The clock frequency (fclk) determines the LCD frame
frequency and the maximum rate for data reception from
the I2C-bus. To allow I2C-bus transmissions at their
maximum data rate of 100 kHz, fclk should be chosen to be
above 125 kHz.
A clock signal must always be supplied to the device;
removing the clock may freeze the LCD in a DC state.
6.6
Timing
The timing of the PCF8576C organizes the internal data
flow of the device. This includes the transfer of display data
from the display RAM to the display segment outputs. In
cascaded applications, the synchronization signal SYNC
maintains the correct timing relationship between the
PCF8576Cs in the system. The timing also generates the
LCD frame frequency which it derives as an integer
multiple of the clock frequency (see Table 3). The frame
frequency is set by the MODE SET commands when
internal clock is used, or by the frequency applied to pin 4
when external clock is used.
The ratio between the clock frequency and the LCD frame
frequency depends on the mode in which the device is
operating. In the power-saving mode the reduction ratio is
six times smaller; this allows the clock frequency to be
reduced by a factor of six. The reduced clock frequency
results in a significant reduction in power dissipation.
The lower clock frequency has the disadvantage of
increasing the response time when large amounts of
display data are transmitted on the I2C-bus.
When a device is unable to digest a display data byte
before the next one arrives, it holds the SCL line LOW until
the first display data byte is stored. This slows down the
transmission rate of the I2C-bus but no data loss occurs.
6.7
Display latch
The display latch holds the display data while the
corresponding multiplex signals are generated. There is a
one-to-one relationship between the data in the display
latch, the LCD segment outputs and one column of the
display RAM.
6.8
Shift register
The shift register serves to transfer display information
from the display RAM to the display latch while previous
data is displayed.
6.9
Segment outputs
The LCD drive section includes 40 segment outputs
S0 to S39 (pins 17 to 56) which should be connected
directly to the LCD. The segment output signals are
generated in accordance with the multiplexed backplane
signals and with data resident in the display latch. When
less than 40 segment outputs are required the unused
segment outputs should be left open-circuit.
6.10
Backplane outputs
The LCD drive section includes four backplane outputs
BP0 to BP3 which should be connected directly to the
LCD. The backplane output signals are generated in
accordance with the selected LCD drive mode. If less than
four backplane outputs are required the unused outputs
can be left open-circuit. In the 1 : 3 multiplex drive mode
BP3 carries the same signal as BP1, therefore these two
adjacent outputs can be tied together to give enhanced
drive capabilities. In the 1 : 2 multiplex drive mode BP0
and BP2, BP1 and BP3 respectively carry the same
signals and may also be paired to increase the drive
capabilities. In the static drive mode the same signal is
carried by all four backplane outputs and they can be
connected in parallel for very high drive requirements.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 935264071026 | LIQUID CRYSTAL DISPLAY DRIVER, UUC56 |
| 06771.25 | Axial Lead and Cartridge Fuses - Ceramic Body |
| 06773.15 | Axial Lead and Cartridge Fuses - Ceramic Body |
| 06852 | CAPACITOR, 250V, 0.61 uF, +-10% |
| 06852-14 | CAPACITOR, 250V, 0.61 uF, +-10% |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 935264217557 | 制造商:NXP Semiconductors 功能描述:SUB ONLY IC |
| 935267356112 | 制造商:NXP Semiconductors 功能描述:IC TEA1507PN |
| 935268081112 | 制造商:NXP Semiconductors 功能描述:SUB ONLY IC |
| 935268721125 | 制造商:NXP Semiconductors 功能描述:Buffer/Line Driver 1-CH Non-Inverting 3-ST CMOS 5-Pin TSSOP T/R |
| 935269304128 | 制造商:ST-Ericsson 功能描述:IC AUDIO CODEC W/TCH SCRN 48LQFP |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。