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參數(shù)資料
| 型號： | 935263812118 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 總線收發(fā)器 |
| 英文描述： | QUAD 1-BIT TRANSCEIVER, TRUE OUTPUT, PDSO16 |
| 封裝： | PLASTIC, SOT-403, TSSOP-16 |
| 文件頁數(shù)： | 4/11頁 |
| 文件大小： | 88K |
| 代理商： | 935263812118 |
Philips Semiconductors
Product specification
GTL2004
Quad GTL/GTL+ to LVTTL/TTL
bidirectional latched translator
2
2000 Jun 19
853–2165 23902
FEATURES
Operates as a quad GTL/GTL+ sampling receiver or as a
LVTTL/TTL to GTL/GTL+ driver
Quad bidirectional bus interface
Separate latch enable for each bit
Live insertion/extraction permitted
B outputs include 30 series resistance
Latch-up protection exceeds 500 mA per JESD78
ESD protection exceeds 2000 V HBM per JESD22-A114 and
1000 V CDM per JESD22-CC101
DESCRIPTION
The GTL2004 is a quad translating transceiver designed for 3.3V
system interface with a GTL/GTL+ bus.
The direction pin allows the part to function as either a GTL to TTL
sampling receiver or as a TTL to GTL interface. Separate latch
enables allow sampling and holding of data from the GTL bus.
PIN CONFIGURATION
16
15
14
13
12
10
11
9
8
7
6
5
4
3
2
1
A0
LE3
GTLREF
B3
B2
B1
B0
DIR
VCC
GND
A3
LE2
A2
LE1
A1
LE0
SW00318
PIN DESCRIPTION
PIN NUMBER
SYMBOL
NAME AND FUNCTION
15
DIR
Direction control input
1, 3, 5, 7
A0 – A3
Data inputs/outputs (A side, GTL)
11, 12, 13, 14
B0 – B3
Data inputs/outputs (B side, TTL)
2, 4, 6, 9
LE0 – LE3
Latch enables
10
GTLREF
GTL reference voltage
8
GND
Ground (0 V)
16
VCC
Positive supply voltage
QUICK REFERENCE DATA
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
SYMBOL
PARAMETER
Tamb = 25°C
B to A
A to B
UNIT
tPLH
tPHL
Propagation delay
An to Bn or Bn to An
CL = 50 pF; VCC = 3.3 V
2.0
1.8
4.4
4.7
ns
CIN
Input capacitance DIR, LEn
VI = 0 V or VCC
3.0
pF
CI/O
I/O pin capacitance
Outputs disabled; VI/O = 0 V or 3.152 V
7.2
4.6
pF
ORDERING INFORMATION
PACKAGES
TEMPERATURE RANGE
ORDER CODE
DWG NUMBER
16-Pin Plastic TSSOP Type II
–40
°C to +85°C
GTL2004 PW DH
SOT403-1
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