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參數資料
| 型號： | 935263696112 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 總線收發(fā)器 |
| 英文描述： | CBT/FST/QS/5C/B SERIES, 10 1-BIT DRIVER, TRUE OUTPUT, PDSO24 |
| 封裝： | PLASTIC, SOT-355, TSSOP-24 |
| 文件頁數： | 5/10頁 |
| 文件大?。?/td> | 113K |
| 代理商： | 935263696112 |
Philips Semiconductors
Product specification
CBT3384
10-bit bus switch with 5-bit output enables
and Schottky undershoot protection
2000 Jan 28
4
DC ELECTRICAL CHARACTERISTICS
LIMITS
SYMBOL
PARAMETER
TEST CONDITIONS
Tamb = –40°C to +85°C
UNIT
Min
Typ1
Max
VIK
Input clamp voltage
VCC = 4.5 V; II = –18 mA
–1.2
V
II
Input leakage current
VCC = 5.5 V; VI = GND or 5.5 V
±1
A
ICC
Quiescent supply current2
VCC = 5.5 V; IO = 0, VI = VCC or GND
3
A
ICC
Additional supply current per input pin2
VCC = 5.5 V, one input at 3.4 V, other inputs at VCC
or GND
2.5
mA
CI
Control pins
VI= 3.0 V or 0
4
pF
CI(OFF)
Power-off leakage current
VO = 3.0 V or 0, OE = VCC
10
pF
3
VCC = 4.5 V; VI = 0 V; II = 64 mA
5
7
ron3
On-resistance
VCC = 4.5 V; VI = 0 V; II = 30 mA
5
7
VCC = 4.5 V; VI = 2.4 V; II = –15 mA
10
15
VP
Pass voltage
VI= VCC = 5.0 V; IO = –100 A
3.4
3.6
3.9
V
IUCP
Undershoot static current protection
VCC = 5.0 V, IB = 400 A; OE = 5.0 V; VB ≥ 3.0 V
8
mA
NOTES:
1. All typical values are at VCC = 5 V, TA = 25°C
2. This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND
3. Measured by the voltage drop between the A and the B terminals at the indicated current through the switch. On-state resistance is
determined by the lowest voltage of the two (A or B) terminals.
AC CHARACTERISTICS
GND = 0 V; tR; CL = 50 pF
FROM
TO
LIMITS
SYMBOL
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC = +5.0 V ±0.5 V
UNIT
(INPUT)
(OUTPUT)
Min
Max
tpd
Propagation delay1
A or B
B or A
.25
ns
ten
Output enable time
to High and Low level
OE
A or B
1.0
5.7
ns
tdis
Output disable time
from High and Low level
OE
A or B
1.0
5.2
ns
NOTE:
1. This parameter is warranted but not production tested. The propagation delay is based on the RC time constant of the typical on–state
resistance of the switch and a load capacitance of 50 pF, when driven by an ideal voltage source (zero output impedance).
LIMITS
SYMBOL
PARAMETER DESCRIPTION
–40
° C/+85° VCC = 5 V, ±0.5 V
UNIT
MIN.
MEAN
MAX.
Tpd
Propagation delay (see Note 1)
250
pS
TPZH
Output enable time to High level
1.6
3.4
5.6
nS
TPHZ
Output enable time from High level
1.7
3.3
5.5
nS
TPZL
Output enable time to Low level
2.3
4
6
nS
TPLZ
Output enable time from Low level
2.5
4.5
6.6
nS
NOTE:
1. This parameter is warranted but not production tested. The propagation delay is based on the RC time constant of the typical on-state
resistance of the switch and a load capacitance of 50 pF, when driven by an ideal voltage source (zero output impedance); at +25
°C.
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