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參數(shù)資料
| 型號： | 935263686551 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 6 CHANNEL(S), 200M bps, SERIAL COMM CONTROLLER, PQFP64 |
| 封裝： | 10 X 10 MM, 1.40 MM HEIGHT, PLASTIC, SOT-314-2, LQFP-64 |
| 文件頁數(shù)： | 8/22頁 |
| 文件大?。?/td> | 170K |
| 代理商： | 935263686551 |
Philips Semiconductors
Preliminary specification
PDI1394P11A
3-port physical layer interface
1999 Mar 10
16
20.0
STATUS REQUEST, LENGTH OF STREAM: 16 BITS
BIT(S)
NAME
DESCRIPTION
0
Arbitration reset gap
Indicates that the phy has detected that the bus has been idle for an arbitration reset gap time (this time is
defined in the P1394 standard). This bit is used by the link in its busy/retry state machine.
1
Subaction gap
Indicates that the phy has detected that the bus has been idle for a subaction gap time (this time is defined
in the P1394 standard). This bit is used by the link to detect the completion of an isochronous cycle.
2
Bus Reset
Indicates that the phy has entered the bus reset state.
3
State Time out or
CPS
Indicates that the phy stayed in a particular state for too long a period, which is usually the effect of a loop
in the cable topology, or that the cable power has dropped below the threshold for reliable operation.
4–7
Address
These bits hold the address of the phy register whose contents will be transferred to the link.
8–15
Data
The data that is to be sent to the link.
21.0
STATUS TRANSFER TIMING
00
01
SV00233
PHY
CTL [0:1]
01
00
S[0,1]
S[2,3]
PHY
D [0:1]
S[14,15]
00
Figure 9.
Status Transfer Timing
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