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參數(shù)資料
| 型號： | 935263625026 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 顯示驅(qū)動器 |
| 英文描述： | LIQUID CRYSTAL DISPLAY DRIVER, U |
| 封裝： | DIE-40 |
| 文件頁數(shù)： | 11/40頁 |
| 文件大?。?/td> | 243K |
| 代理商： | 935263625026 |
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1998 May 04
19
Philips Semiconductors
Product specication
Universal LCD driver for low multiplex
rates
PCF8566
7.5
PCF8566 I2C-bus controller
The PCF8566 acts as an I2C-bus slave receiver. It does
not initiate I2C-bus transfers or transmit data to an I2C-bus
master receiver. The only data output from the PCF8566
are the acknowledge signals of the selected devices.
Device selection depends on the I2C-bus slave address,
on the transferred command data and on the hardware
subaddress.
In single device applications, the hardware subaddress
inputs A0, A1 and A2 are normally left open-circuit or tied
to VSS which defines the hardware subaddress 0.
In multiple device applications A0, A1 and A2 are left
open-circuit or tied to VSS or VDD according to a binary
coding scheme such that no two devices with a common
I2C-bus slave address have the same hardware
subaddress.
In the power-saving mode it is possible that the PCF8566
is not able to keep up with the highest transmission rates
when large amounts of display data are transmitted. If this
situation occurs, the PCF8566 forces the SCL line LOW
until its internal operations are completed. This is known
as the ‘clock synchronization feature’ of the I2C-bus and
serves to slow down fast transmitters. Data loss does not
occur.
7.6
Input lters
To enhance noise immunity in electrically adverse
environments, RC low-pass filters are provided on the
SDA and SCL lines.
7.7
I2C-bus protocol
Two I2C-bus slave addresses (0111110 and 0111111) are
reserved for PCF8566. The least-significant bit of the slave
address that a PCF8566 will respond to is defined by the
level tied at its input SA0 (pin 10). Therefore, two types of
PCF8566 can be distinguished on the same I2C-bus which
allows:
1. Up to 16 PCF8566s on the same I2C-bus for very large
LCD applications
2. The use of two types of LCD multiplex on the same
I2C-bus.
The I2C-bus protocol is shown in Fig.15. The sequence is
initiated with a START condition (S) from the I2C-bus
master which is followed by one of the two PCF8566 slave
addresses available. All PCF8566s with the corresponding
SA0 level acknowledge in parallel the slave address but all
PCF8566s with the alternative SA0 level ignore the whole
I2C-bus transfer. After acknowledgement, one or more
command bytes (m) follow which define the status of the
addressed PCF8566s. The last command byte is tagged
with a cleared most-significant bit, the continuation bit C.
The command bytes are also acknowledged by all
addressed PCF8566s on the bus.
After the last command byte, a series of display data bytes
(n) may follow. These display data bytes are stored in the
display RAM at the address specified by the data pointer
and the subaddress counter. Both data pointer and
subaddress counter are automatically updated and the
data are directed to the intended PCF8566 device.
The acknowledgement after each byte is made only by the
(A0, A1, A2) addressed PCF8566. After the last display
byte, the I2C-bus master issues a STOP condition (P).
7.8
Command decoder
The command decoder identifies command bytes that
arrive on the I2C-bus. All available commands carry a
continuation bit C in their most-significant bit position
(see Fig.16). When this bit is set, it indicates that the next
byte of the transfer to arrive will also represent a
command.
If the bit is reset, it indicates the last command byte of the
transfer. Further bytes will be regarded as display data.
The five commands available to the PCF8566 are defined
in Table 5.
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