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參數(shù)資料
| 型號： | 935263563118 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 門電路 |
| 英文描述： | AHC SERIES, QUAD 2-INPUT XOR GATE, PDSO14 |
| 封裝： | 3.90 MM, PLASTIC, SOT-108-1, SO-14 |
| 文件頁數(shù)： | 9/16頁 |
| 文件大?。?/td> | 75K |
| 代理商： | 935263563118 |
1999 Sep 17
2
Philips Semiconductors
Product specication
Quad 2-input EXCLUSIVE-OR gate
74AHC86; 74AHCT86
FEATURES
ESD protection:
HBM EIA/JESD22-A114-A
exceeds 2000 V
MM EIA/JESD22-A115-A
exceeds 200 V
CDM EIA/JESD22-C101
exceeds 1000 V
Inputs accepts voltages higher than
VCC
For AHC only:
operates with CMOS input levels
For AHCT only:
operates with TTL input levels
Specified from 40 to +85 °C and
40 to +125 °C.
DESCRIPTION
The 74AHC/AHCT86 are high-speed
Si-gate CMOS devices and are pin
compatible with Low power Schottky
TTL (LSTTL). They are specified in
compliance with JEDEC standard
no. 7A.
The 74AHC/AHCT86 provides the
2-input EXCLUSIVE-OR function.
QUICK REFERENCE DATA
Ground = 0 V; Tamb =25 °C; tr =tf ≤ 3.0 ns.
Notes
1. CPD is used to determine the dynamic power dissipation (PD in W).
PD =CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
∑ (CL × VCC2 × fo) = sum of outputs;
CL = output load capacitance in pF;
VCC = supply voltage in Volts.
2. The condition is VI = GND to VCC.
FUNCTION TABLE
See note 1.
Note
1. H = HIGH voltage level;
L = LOW voltage level.
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
AHC
AHCT
tPHL/tPLH
propagation delay
nA, nB to nY
CL =15pF;
VCC =5V
3.4
ns
CI
input capacitance
VI =VCC or GND
3.0
pF
CO
output capacitance VI =VCC or GND
4.0
pF
CPD
power dissipation
capacitance
CL =50pF;
f = 1 MHz;
notes 1 and 2
10
12
pF
INPUT
OUTPUT
nA
nB
nY
LLL
LH
H
HLH
HH
L
ORDERING INFORMATION
OUTSIDE NORTH
AMERICA
NORTH AMERICA
PACKAGES
PINS
PACKAGE
MATERIAL
CODE
74AHC86D
14
SO
plastic
SOT108-1
74AHC86PW
74AHC86PW DH
14
TSSOP
plastic
SOT402-1
74AHCT86D
14
SO
plastic
SOT108-1
74AHCT86PW
74AHCT86PW DH
14
TSSOP
plastic
SOT402-1
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