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參數(shù)資料
| 型號(hào)： | 935263358512 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, OTPROM, 20 MHz, MICROCONTROLLER, PDSO20 |
| 封裝： | 7.50 MM, SO-20 |
| 文件頁數(shù)： | 41/58頁 |
| 文件大?。?/td> | 312K |
| 代理商： | 935263358512 |
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Philips Semiconductors
Preliminary specification
87LPC764
Low power, low price, low pin count (20 pin)
microcontroller with 4 kB OTP
2000 Jun 01
43
EPROM Characteristics
Programming of the EPROM on the 87LPC764 is accomplished with
a serial programming method. Commands, addresses, and data are
transmitted to and from the device on two pins after programming
mode is entered. Serial programming allows easy implementation of
in-circuit programming of the 87LPC764 in an application board.
Details of the programming algorithm may be found in a separate
document that is available on the Philips web site at:
http://www.semiconductors.philips.com/mcu/support/progspecs/
The 87LPC764 contains three signature bytes that can be read and
used by an EPROM programming system to identify the device. The
signature bytes designate the device as an 87LPC764 manufactured
by Philips. The signature bytes may be read by the user program at
addresses FC30h, FC31h and FC60h with the MOVC instruction,
using the DPTR register for addressing.
A special user data area is also available for access via the MOVC
instruction at addresses FCE0h through FCFFh. This “customer
code” space is programmed in the same manner as the main code
EPROM and may be used to store a serial number, manufacturing
date, or other application information.
32-Byte Customer Code Space
A small supplemental EPROM space is reserved for use by the
customer in order to identify code revisions, store checksums, add a
serial number to each device, or any other desired use. This area
exists in the code memory space from addresses FCE0h through
FCFFh. Code execution from this space is not supported, but it may
be read as data through the use of the MOVC instruction with the
appropriate addresses. The memory may be programmed at the
same time as the rest of the code memory and UCFG bytes are
programmed.
System Configuration Bytes
A number of user configurable features of the 87LPC764 must be
defined at power up and therefore cannot be set by the program after
start of execution. Those features are configured through the use of
two EPROM bytes that are programmed in the same manner as the
EPROM program space. The contents of the two configuration bytes,
UCFG1 and UCFG2, are shown in Figures 36 and 37. The values of
these bytes may be read by the program through the use of the
MOVX instruction at the addresses shown in the figure.
BIT
SYMBOL
FUNCTION
UCFG1.7
WDTE
Watchdog timer enable. When programmed (0), disables the watchdog timer. The timer may
still be used to generate an interrupt.
UCFG1.6
RPD
Reset pin disable. When 1 disables the reset function of pin P1.5, allowing it to be used as an
input only port pin.
UCFG1.5
PRHI
Port reset high. When 1, ports reset to a high state. When 0, ports reset to a low state.
UCFG1.4
BOV
Brownout voltage select. When 1, the brownout detect voltage is 2.5V. When 0, the brownout
detect voltage is 3.8V. This is described in the Power Monitoring Functions section.
UCFG1.3
CLKR
Clock rate select. When 0, the CPU clock rate is divided by 2. This results in machine cycles
taking 12 CPU clocks to complete as in the standard 80C51. For full backward compatibility,
this division applies to peripheral timing as well.
UCFG1.2–0 FOSC2–FSOC0
CPU oscillator type select. See Oscillator section for additional information. Combinations
other than those shown below should not be used. They are reserved for future use.
FOSC2–FOSC0
Oscillator Configuration
1 1 1
External clock input on X1 (default setting for an unprogrammed part).
0 1 1
Internal RC oscillator, 6 MHz
±25%.
0 1 0
Low frequency crystal, 20 kHz to 100 kHz.
0 0 1
Medium frequency crystal or resonator, 100 kHz to 4 MHz.
0 0 0
High frequency crystal or resonator, 4 MHz to 20 MHz.
FOSC0
SU01185
FOSC1
FOSC2
CLKR
BOV
PRHI
RPD
WDTE
0
1
2
3
4
5
6
7
UCFG1
Unprogrammed Value: FFh
Address: FD00h
Figure 36. EPROM System Configuration Byte 1 (UCFG1)
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