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參數(shù)資料
| 型號： | 935262321518 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 顏色信號轉(zhuǎn)換 |
| 英文描述： | COLOR SIGNAL ENCODER, PQFP44 |
| 封裝： | PLASTIC, QFP-44 |
| 文件頁數(shù)： | 13/43頁 |
| 文件大?。?/td> | 193K |
| 代理商： | 935262321518 |
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1999 May 31
20
Philips Semiconductors
Product specication
Digital video encoder
SAA7126H; SAA7127H
Table 30 Subaddress 6DH
Table 31 Subaddress 6EH
Table 32 Logic levels and function of PHRES
Table 33 Logic levels and function of LDEL
Table 34 Logic levels and function of FLC
DATA BYTE
DESCRIPTION
VTRIG
sets the vertical trigger phase related to signal on RCV1 input
increasing VTRIG decreases delays of all internally generated timing signals, measured in half lines;
variation range of VTRIG=0to31 (1FH)
DATA BYTE
LOGIC
LEVEL
DESCRIPTION
SBLBN
0
vertical blanking is dened by programming of FAL and LAL; default after reset
1
vertical blanking is forced in accordance with
“CCIR 624” (50 Hz) or RS170A (60 Hz)
BLCKON
0
encoder in normal operation mode
1
output signal is forced to blanking level; default after reset
PHRES
selects the phase reset mode of the colour subcarrier generator; see Table 32
LDEL
selects the delay on luminance path with reference to chrominance path; see Table 33
FLC
eld length control; see Table 34
DATA BYTE
DESCRIPTION
PHRES1
PHRES0
0
no reset or reset via RTCI from SAA7111 if bit RTCE = 1; default after reset
0
1
reset every two lines
1
0
reset every eight elds
1
reset every four elds
DATA BYTE
DESCRIPTION
LDEL1
LDEL0
0
no luminance delay; default after reset
0
1
1 LLC luminance delay
1
0
2 LLC luminance delay
1
3 LLC luminance delay
DATA BYTE
DESCRIPTION
FLC1
FLC0
0
interlaced 312.5 lines/eld at 50 Hz, 262.5 lines/eld at 60 Hz; default after reset
0
1
non-interlaced 312 lines/eld at 50 Hz, 262 lines/eld at 60 Hz
1
0
non-interlaced 313 lines/eld at 50 Hz, 263 lines/eld at 60 Hz
1
non-interlaced 313 lines/eld at 50 Hz, 263 lines/eld at 60 Hz
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