參數(shù)資料
型號(hào)： 935262254557
廠商： NXP SEMICONDUCTORS
元件分類： ADC
英文描述： 3-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQFP100
封裝： PLASTIC, SOT-317-2, QFP-64
文件頁(yè)數(shù)： 18/40頁(yè)
文件大小： 250K
代理商： 935262254557
1999 Feb 24
25
Philips Semiconductors
Product specication
Triple high-speed Analog-to-Digital
Converter (ADC)
TDA8752A
tCOAST(max)
maximum coast mode time
40
lines
trecap
PLL recapture time
when coast mode is aborted
3
lines
tcap
PLL capture time
in start-up conditions
5ms
Φstep
phase shift step
Tamb =25 °C
11.25
deg
ADCs
fs
maximum sampling frequency
TDA8752A/6
60
MHz
TDA8752A/8
100
MHz
INL
DC integral non linearity
from IC analog input to
digital output; ramp input;
fCLK = 100 MHz
±0.5
±1.5
LSB
DNL
DC differential non linearity
from IC analog input to
digital output; ramp input;
fCLK = 100 MHz
±0.5
±1.0
LSB
ENOB
effective number of bits
from IC analog input to
digital output; 10 kHz sine
wave input; ramp input;
fCLK = 100 MHz; note 1
7.4
bits
Signal-to-noise ratio
S/N
signal-to-noise ratio
maximum gain;
fCLK = 100 MHz
45
dB
minimum gain;
fCLK = 100 MHz
44
dB
Spurious free dynamic range
SFDR
spurious free dynamic range
maximum gain;
fCLK = 100 MHz
60
dB
minimum gain;
fCLK = 100 MHz
60
dB
Clock timing output (CKADCO, CKBO and CKAO)
ηext
ADC clock duty cycle
100 MHz output
45
50
55
%
fCLK(max)
maximum clock frequency
100
MHz
Clock timing input (CKEXT)
fCLK(max)
maximum clock frequency
100
MHz
tCPH
clock pulse width HIGH
3.6
ns
tCPL
clock pulse width LOW
4.5
ns
td(CLKO)
delay from CKEXT to
CKADCO
INV set to LOW
13.6
14.7
15.2
ns
INV set to HIGH
ns
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
14.7
t
CLK
2
-----------
+
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