參數(shù)資料
型號(hào)： 935261790112
廠商： NXP SEMICONDUCTORS
元件分類(lèi)： 消費(fèi)家電
英文描述： SPECIALTY CONSUMER CIRCUIT, PDSO28
封裝： 5.30 MM, PLASTIC, SSOP-28
文件頁(yè)數(shù)： 31/31頁(yè)
文件大小： 199K
代理商： 935261790112
2000 Feb 04
9
Philips Semiconductors
Preliminary specication
Low-voltage low-power stereo audio
CODEC with DSP features
UDA1344TS
Static pin mode
The UDA1344TS is set to static pin mode by setting both
pins MC1 and MC2 to HIGH level.
The controllable features in this mode are:
System clock frequency selection
Data input/output format selection
De-emphasis and mute control
Power-down and ADC input level selection.
PINNING DEFINITION
The pinning definition in the static pin mode is given in
Table 6.
Table 6
Pinning denition in static pin model
SYSTEM CLOCK
In the static pin mode the options are 256fs and 384fs as
given in Table 7.
Table 7
System clock selection
MUTE AND DE-EMPHASIS
The level definition of pin MP2 pin is given in Table 8.
Table 8
Levels for pin MP2
INPUT/OUTPUT DATA FORMAT SELECTION
The input/output data format can be selected using
pins MP1 and MP5 as given in Table 9.
Table 9
Data format selection
ADC INPUT VOLTAGE SELECTION AND POWER-DOWN
In the static pin mode the three-level pin MP4 is used to
select 0 or 6 dB gain and power-down.
Table 10 Levels for pin MP4
PIN
DESCRIPTION
MP1
data input/output setting
MP2
three-level pin to select no
de-emphasis, de-emphasis or mute
MP3
256fs or 384fs system clock selection
MP4
three-level pin to select
ADC power-down, ADC input
1 V (RMS) or ADC input 2 V (RMS)
MP5
data input/output setting
PIN MP3
SELECTION
LOW
256fs clock frequency
HIGH
384fs clock frequency
PIN MP2
SELECTION
LOW
no de-emphasis and mute
0.5VDDD
de-emphasis 44.1 kHz
HIGH
mute
PIN MP1 PIN MP5
SELECTION
LOW
input: MSB-justied
LOW
HIGH
input: I2S-bus
HIGH
LOW
input: LSB-justied 20 bits;
output: MSB-justied
HIGH
input: LSB-justied 16 bits;
output: MSB-justied
PIN MP4
SELECTION
LOW
ADC power-down
0.5VDDD
6 dB gain
HIGH
0 dB gain
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