參數(shù)資料
型號： 935222940112
廠商： NXP SEMICONDUCTORS
元件分類： 微控制器/微處理器
英文描述： 8-BIT, 24 MHz, MICROCONTROLLER, PQCC44
封裝： PLASTIC, LCC-44
文件頁數(shù)： 50/80頁
文件大?。?/td> 446K
代理商： 935222940112
1997 Dec 15
54
Philips Semiconductors
Product specication
8-bit microcontrollers
P83C524; P80C528; P83C528
Notes to the DC characteristics
1. Conditions for:
a) The operating supply current is measured with all output pins disconnected; XTAL1 driven with tr =tf = 5 ns;
VIL =VSS +0.5 V; VIH =VDD 0.5 V; XTAL2 not connected; EA = RST = Port 0 = P1.6 = P1.7 = VDD;
the WDT is disabled (by the external RESET).
2. Conditions for:
a) The Idle mode supply current is measured with all output pins disconnected; XTAL1 driven with tr =tf = 5 ns;
VIL =VSS +0.5 V; VIH =VDD 0.5 V; XTAL2 not connected; the WDT is disabled; EA = RST = VSS;
Port 0 = P1.6 = P1.7 = VDD.
3. Conditions for:
a) The Power-down current is measured with all output pins disconnected; XTAL2 not connected;
WDT is disabled; EA = RST = XTAL1 = VSS; Port 0 = P1.6 = P1.7 = VDD.
4. Capacitive loading on Port 0 and Port 2 may cause spurious noise pulses to be superimposed on the LOW level
output voltage of ALE, Port 1 and Port 3. The noise is due to external bus capacitance discharging into the Port 0
and Port 2 pins when these pins make a HIGH-to-LOW transition during bus operations. In the worst cases
(capacitive loading
> 100pF), the noise pulse on the ALE line may exceed 0.8 V. In such cases it may be desirable
to qualify ALE with a Schmitt Trigger, or use an address latch with a Schmitt Trigger STROBE input.
5. Capacitive loading on Port 0 and Port 2 may cause the HIGH level output voltage on ALE and PSEN to momentarily
fall below the 0.9 VDD specification when the address bits are stabilizing.
6. The input threshold voltage of P1.6 and P1.7 (SIO1) meets the I2C specification, so a voltage below 0.3 VDD will be
recognized as a logic 0 while an input above 0.7 VDD will be recognized as a logic 1.
7. Under steady state (non-transient) conditions, IOL must be externally limited as follows:
a) Maximum IOL per port pin:10 mA.
b) Maximum IOL per 8-bit port:- Port 0: 26 mA; Ports 1, 2 and 3: 15 mA.
c) Maximum total IOL for all output pins: 71 mA. If IOL exceeds the test condition,
VOL may exceed the related specification.
d) Pins are not guaranteed to sink current greater than the listed test conditions.
8. IDD max. at other frequencies can be derived from Fig.26 where f is the external oscillator frequency in MHz;
IDD max. is given in mA.
VOH1
HIGH level output voltage
Port0in in external bus mode,
ALE, PSEN, RST
IOH = 800 A;
VDD =5V± 10%
IOH = 300 A;
IOH = 80 A; note 5
2.4
0.75VDD
0.9VDD
V
RRST
RST pull
down resistor
50
150
k
CI/O
I/O pin capacitance
test frequency = 1 MHz;
Tamb =25 °C
10
pF
SYMBOL
PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
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