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參數(shù)資料
| 型號： | 935222920112 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, 24 MHz, MICROCONTROLLER, PDIP40 |
| 封裝： | 0.600 INCH, PLASTIC, DIP-40 |
| 文件頁數(shù)： | 39/80頁 |
| 文件大?。?/td> | 446K |
| 代理商： | 935222920112 |
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1997 Dec 15
44
Philips Semiconductors
Product specication
8-bit microcontrollers
P83C524; P80C528; P83C528
16 OSCILLATOR CIRCUIT
The oscillator circuit of the P83C528 is a single-stage
inverting amplifier in a Pierce oscillator configuration. The
circuitry between the XTAL1 and XTAL2 is basically an
inverter biased to the transfer point. Either a crystal or
ceramic resonator can be used as the feedback element to
complete the oscillator circuitry. Both are operated in
parallel resonance. XTAL1 is the high gain amplifier input,
and XTAL2 is the output (see Fig.22). To drive the
P83C528 externally, XTAL1 is driven from an external
source and XTAL2 left open-circuit (see Fig.23).
Fig.22 P83C528 oscillator circuit.
handbook, halfpage
C1
XTAL1
XTAL2
20 pF
C2
MBC473
20 pF
Fig.23 Driving the P83C528 from an
external source.
handbook, halfpage
XTAL1
XTAL2
MBC472
external clock
(not TTL compatible)
not connected
17 RESET CIRCUIT
The reset circuitry for the P83C528 is connected to the
reset pin RST. A Schmitt trigger is used at the input for
noise rejection. The output of the Schmitt trigger is
sampled by the reset circuitry every machine cycle.
A reset is accomplished by holding the RST pin HIGH for
at least two machine cycles (24 oscillator periods). The
CPU responds by executing an internal reset. During reset
ALE and PSEN output a HIGH level. In order to perform a
correct reset, this level must not be affected by external
elements.
With the P83C528, the RST line can also be pulled HIGH
internally by a pull-up transistor activated by the WDT T3.
The length of the reset pulse from T3 is 16 x 2048 cycles
of the on-chip watchdog oscillator. If the WDT is also used
to reset external devices, the usual capacitor arrangement
should not be connected to RST pin. Instead, an extra
circuit should be used to perform the Power-on Reset
operation. It should be remembered that a Timer T3
overflow, if enabled, will force a reset condition to the
P83C528 by an internal connection, whether the output
RST is tied LOW or not (see Fig.24).
The internal reset is executed during the second cycle in
which RST is pulled HIGH and is repeated every cycle until
RST goes LOW. It leaves the internal registers as shown
by Table 29.
Fig.24 On-chip reset configuration.
handbook, halfpage
MBC476 - 1
SCHMITT
TRIGGER
RESET
CIRCUITRY
overflow
timer T3
VDD
RST
on-chip
resistor
RST
R
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