參數(shù)資料
型號(hào)： 935205860118
廠商： NXP SEMICONDUCTORS
元件分類： PLL合成/DDS/VCOs
英文描述： PLL FREQUENCY SYNTHESIZER, 1400 MHz, PDSO20
封裝： 4.40 MM, PLASTIC, SSOP-20
文件頁(yè)數(shù)： 20/23頁(yè)
文件大?。?/td> 257K
代理商： 935205860118
1996 Dec 17
6
Philips Semiconductors
Product specication
1.4 GHz I2C-bus controlled multimedia
synthesizer
TSA5523M
FUNCTIONAL DESCRIPTION
The device is controlled via the two-wire I2C-bus.
For programming, there is one module address (7 bits)
and the R/W bit for selecting the read or the write mode.
Write mode: R/W=0 (see Table 1)
After the address transmission (first byte), data bytes can
be sent to the device. Four data bytes are needed to fully
program the device. The bus transceiver has an
auto-increment facility which permits the programming of
the device within one single transmission
(address + 4 data bytes).
The device can also be partially programmed providing
that the first data byte following the address is Divider
Byte 1 (DB1) or Control Byte (CB). The meaning of the bits
in the data bytes is given in Table 1.
The first bit of the first data byte transmitted indicates
whether frequency data (first bit = 0) or control and ports
data (first bit = 1) will follow. Until an I2C-bus STOP
condition is sent by the controller, additional data bytes
can be entered without the need to re-address the device.
The frequency register is loaded after the 8th clock pulse
of the second Divider Byte (DB2), the control register is
loaded after the 8th clock pulse of the control byte and the
ports register is loaded after the 8th clock pulse of the
Ports Byte (PB).
I2C-bus address selection
The module address contains programmable address bits
(MA1 and MA0) which offer the possibility of having
several synthesizers (up to 4) in one system by applying a
specific voltage to the AS input. The relationship between
MA1 and MA0 and the input voltage on the AS input is
given in Table 2.
Table 1
I2C-bus data format
Note
1. A = Acknowledge.
Table 2
Explanation to Table 1
DATA BYTES
MSB
LSB
ACK
Address Byte (ADR)
11000
MA1
MA0
0
A(1)
Divider Byte 1 (DB1)
0
N14
N13
N12
N11
N10
N9
N8
A(1)
Divider Byte 2 (DB2)
N7
N6
N5
N4
N3
N2
N1
N0
A(1)
Control Byte (CB)
1
CP
T2
T1
T0
RSA
RSB
OS
A(1)
Ports Byte (PB)
P7
P6
P5
P4
P3
P2
P1
P0
A(1)
SYMBOL
DESCRIPTION
MA1 and MA0
programmable address bits (see Table 3)
N14 to N0
programmable divider bits N = N14
× 214 +213 + ... + N1 × 2+N0
CP
charge-pump current
CP = 0
50
A
CP = 1
250
A
T2, T1 and T0
test bits; normal operation; T2 = 0, T1 = 0, T0 = 1 (see Table 4)
RSA and RSB
reference divider ratio select bits (see Table 5)
OS
tuning amplier control bit
OS = 0
normal operation; tuning voltage is ON
OS = 1
tuning voltage is OFF (high impedance), IDC output voltage is LOW
P7 to P0
NPN open-collector control bits
Pn = 0
output n is OFF
Pn = 1
output n is ON
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