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參數(shù)資料
| 型號： | 935200650118 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 計數(shù)器 |
| 英文描述： | 4000/14000/40000 SERIES, ASYN NEGATIVE EDGE TRIGGERED 14-BIT UP BINARY COUNTER, PDSO16 |
| 封裝： | PLASTIC, SOT-109, SO-16 |
| 文件頁數(shù)： | 4/7頁 |
| 文件大?。?/td> | 109K |
| 代理商： | 935200650118 |
January 1995
4
Philips Semiconductors
Product specication
14-stage ripple-carry binary counter/divider
and oscillator
HEF4060B
MSI
AC CHARACTERISTICS
VSS = 0 V; Tamb =25 °C; CL = 50 pF; input transition times ≤ 20 ns
VDD
V
SYMBOL
MIN.
TYP.
MAX.
TYPICAL EXTRAPOLATION
FORMULA
Propagation delays
RS
→ O3
5
210
420
ns
183 ns
+ (0,55 ns/pF) CL
HIGH to LOW
10
tPHL
80
160
ns
69 ns
+ (0,23 ns/pF) CL
15
50
100
ns
42 ns
+ (0,16 ns/pF) CL
5
210
420
ns
183 ns
+ (0,55 ns/pF) CL
LOW to HIGH
10
tPLH
80
160
ns
69 ns
+ (0,23 ns/pF) CL
15
50
100
ns
42 ns
+ (0,16 ns/pF) CL
On → On + 1
525
50
ns
HIGH to LOW
10
tPHL
10
20
ns
15
6
12
ns
525
50
ns
LOW to HIGH
10
tPLH
10
20
ns
15
6
12
ns
MR
→ On
5
100
200
ns
73 ns
+ (0,55 ns/pF) CL
HIGH to LOW
10
tPHL
40
80
ns
29 ns
+ (0,23 ns/pF) CL
15
30
60
ns
22 ns
+ (0,16 ns/pF) CL
Output transition
5
60
120
ns
10 ns
+ (1,0 ns/pF) CL
times
10
tTHL
30
60
ns
9 ns
+ (0,42 ns/pF) CL
HIGH to LOW
15
20
40
ns
6 ns
+ (0,28 ns/pF) CL
5
60
120
ns
10 ns
+ (1,0 ns/pF) CL
LOW to HIGH
10
tTLH
30
60
ns
9 ns
+ (0,42 ns/pF) CL
15
20
40
ns
6 ns
+ (0,28 ns/pF) CL
Minimum clock pulse
5
120
60
ns
width input RS
10
tWRSH
50
25
ns
HIGH
15
30
15
ns
Minimum MR pulse
5
50
25
ns
width; HIGH
10
tWMRH
30
15
ns
15
20
10
ns
Recovery time
5
160
80
ns
for MR
10
tRMR
80
40
ns
15
60
30
ns
Maximum clock pulse
5
4
8
MHz
frequency input RS
10
fmax
10
20
MHz
15
30
MHz
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