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參數(shù)資料
| 型號： | 935189990112 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 門電路 |
| 英文描述： | HC/UH SERIES, HEX 1-INPUT INVERT GATE, PDSO16 |
| 封裝： | SOT-338, 16 PIN |
| 文件頁數(shù)： | 2/7頁 |
| 文件大?。?/td> | 41K |
| 代理商： | 935189990112 |
December 1990
2
Philips Semiconductors
Product specication
Hex inverting high-to-low level shifter
74HC4049
FEATURES
Output capability: standard
ICC category: SSI
GENERAL DESCRIPTION
The 74HC4049 is a high-speed Si-gate CMOS device and
is pin compatible with the “4049” of the “4000B” series. It
is specified in compliance with JEDEC standard no. 7A.
The 74HC4049 provides six inverting buffers with a
modified input protection structure, which has no diode
connected to VCC. Input voltages of up to 15 V may
therefore be used.
This feature enables the inverting buffers to be used as
logic level translators, which will convert high level logic to
low level logic, while operating from a low voltage power
supply. For example 15 V logic (“4000B series”) can be
converted down to 2 V logic.
The actual input switch level remains related to the VCC
and is the same as mentioned in the family characteristics.
At the same time each part can be used as a simple
inverter without level translation.
APPLICATIONS
Converting 15 V logic (“4000B” series) down to 2 V logic.
QUICK REFERENCE DATA
GND = 0 V; Tamb =25 °C; tr =tf = 6 ns
Note
1. CPD is used to determine the dynamic power dissipation (PD in W):
PD =CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) where:
fi = input frequency in MHz
fo = output frequency in MHz
CL = output load capacitance in pF
VCC = supply voltage in V
∑ (CL × VCC2 × fo) = sum of outputs
ORDERING INFORMATION
See
“74HC/HCT/HCU/HCMOS Logic Package Information”.
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
HC
tPHL/tPLH
propagation delay nA to nYCL = 15 pF; VCC = 5 V
8
ns
CI
input capacitance
3.5
pF
CPD
power dissipation capacitance per buffer note 1
14
pF
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